FABulous: an Embedded FPGA Framework

Overview and Features

FABulous is an open-source embedded FPGA (eFPGA) framework for generating FPGA fabric and integrates the open source CAD tools Yosys and nextpnr for the user design flow. It is silicon-proven through multiple successful tapeouts across TSMC 180nm, Skywater 130nm, IHP SG13G2, GF180MCU, and 28nm CMOS, FABulous provides a full-stack toolchain from CSV-based fabric definition to production-ready GDSII. The framework supports frame-based partial reconfiguration for runtime reconfiguration of individual FPGA regions.

Key Capabilities

• Full-stack toolchain -- Integrates Yosys (synthesis), nextpnr (place-and-route), and LibreLane (physical design) for a complete fabric-to-GDSII flow.
• CSV-based fabric definition -- Define custom fabrics through a simple fabric.csv configuration file instead of complex XML architecture descriptions, making customisation accessible to hardware engineers without specialised tooling.
• Modular tile-based architecture -- Compose fabrics from look-up tables (LUTs), memory blocks, DSPs, I/O blocks, and arithmetic units, with full support for user-defined custom primitives.
• Frame-based partial reconfiguration -- Supports frame-based partial reconfiguration, enabling runtime reconfiguration of individual FPGA regions without disrupting the rest of the fabric.
• Multi-process-node portability -- Silicon-proven across 5+ process nodes, demonstrating portability across foundry processes.
• Production-ready GDS flow -- Generate GDSII layout directly from fabric definitions using the integrated OpenROAD flow, ready for ASIC fabrication.
• Apache 2.0 licence -- Freely available for both commercial and academic use.

Silicon Proven

FABulous has been validated through 12+ successful tapeouts across multiple process nodes.

See the Chip Gallery for detailed descriptions and links to each tapeout.

System Requirements

To run FABulous, you need Python 3.12 or later. The framework is fully supported on Linux and macOS. Windows users must utilise the Windows Subsystem for Linux (WSL) for compatibility.

For the complete toolchain experience, you will need synthesis and place-and-route tools. We recommend installing the OSS CAD Suite, which bundles Yosys and nextpnr, using the provided FABulous install oss-cad-suite command. Additionally, using uv is highly recommended for faster Python package management.

Installation

You can install FABulous either directly from the Python Package Index for standard usage or from the source code if you intend to contribute to the development of the framework.

Standard Installation (via PyPI)

pip install fabulous-fpga
# or
# uv tool install fabulous-fpga
FABulous create-project demo
cd demo && FABulous start

Development Installation (from source)

git clone https://github.com/FPGA-Research/FABulous
cd FABulous
uv sync
FABulous create-project demo
cd demo && FABulous start

Once installed, you can automatically install the recommended CAD tools by running FABulous install oss-cad-suite in your terminal.

Codespaces and Dev Container (quick use)

If you want a pre-configured environment without local dependency setup, you can use the provided container workflows:

• GitHub Codespaces: open the repository in Codespaces and use the bundled dev container. GUI tools are exposed through a browser VNC session on port 6080.
• Local Dev Container: open this repository in VS Code and run Dev Containers: Reopen in Container with the Local profile. On Linux, the local profile configures X11 forwarding for GUI tools.

For full step-by-step instructions, see the online docs:

• Codespaces guide: https://fabulous.readthedocs.io/en/latest/getting_started/codespaces.html
• Docker and local dev container guide: https://fabulous.readthedocs.io/en/latest/getting_started/installation/docker.html

Using FABulous

Interacting with FABulous is typically done via its interactive shell or through automated scripts. The outputs are systematically organised into a Fabric directory for generated RTL and a Tile directory for primitive definitions. Bitstreams and logs are stored within your user_design folder.

Essential Commands Table

Typical Interactive Workflow

FABulous> run_fab
FABulous> compile_design user_design/sequential_16bit_en.v
FABulous> exit

GUI Setup with FABulator

FABulator is a companion tool that allows you to visually explore the fabrics generated by FABulous and display user designs. To import a fabric into FABulator, you must first generate a geometry file. You can achieve this by running the following commands within the FABulous shell:

FABulous> gen_fabric
FABulous> gen_geometry

(Note: gen_fabric is only needed once to generate the required switch_matrix.csv files).

Contribution Guidelines

We welcome community contributions. To ensure consistency, please use uv for environment setup, follow Ruff formatting standards, and use conventional commits for your messages. Comprehensive details regarding environment setup and coding standards are available in our Development Guide.

Before opening a pull request, please read CONTRIBUTING.md for the full contribution terms. By submitting a pull request, you agree that your contribution is licensed under the project's Apache 2.0 License and that you have the right to grant this license.

Contributors are recognised automatically in AUTHORS.md, which is regenerated from the GitHub contributors list as part of the release flow.

Citation

If you use FABulous in your academic research, please cite the following publication:

Dirk Koch, Nguyen Dao, Bea Healy, Jing Yu, and Andrew Attwood. 2021. FABulous: An Embedded FPGA Framework. In The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA '21). Association for Computing Machinery, New York, NY, USA, 45–56. DOI: https://doi.org/10.1145/3431920.3439302

Link to Paper

@inproceedings{koch2021fabulous,
  title={FABulous: An embedded FPGA framework},
  author={Koch, Dirk and Dao, Nguyen and Healy, Bea and Yu, Jing and Attwood, Andrew},
  booktitle={The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
  pages={45--56},
  year={2021}
}

FABulous and Alternative Offerings

Disclaimer and Limitation of Liability

Liability

This software is provided "as is" without any express or implied warranty. In no event shall the authors, contributors, copyright holders, or affiliated institutions be liable for any claims, damages, or other liabilities arising from its use.

FABulous is an IP generator framework that produces HDL designs for embedded FPGA fabrics intended for ASIC fabrication. The developers and contributors assume no responsibility or liability for any intellectual property generated using this framework, nor are we responsible for any chips, ASICs, FPGAs, or physical devices fabricated using these designs.

While continuous efforts are made to ensure reliability, and several designs have been silicon-proven, we make no guarantees regarding the functional correctness, timing closure, physical design quality, or manufacturing compliance of the generated IP. Silicon-proven status does not imply that FABulous-generated designs can be used without rigorous verification. Users are solely responsible for performing comprehensive whole-system verification (including timing-annotated and formal verification) to ensure the generated fabric functions correctly for their specific application prior to fabrication. Use of this software and any derived products is entirely at your own risk.

License

For the complete license terms of using the software, see the Apache 2.0 License.