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A processor cache simulator for the MIPS ISA

Project description

Copyright 2015-2018 Caleb Evans
Released under the MIT license

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This program simulates a processor cache for the MIPS instruction set architecture. It can simulate all three fundamental caching schemes: direct-mapped, n-way set associative, and fully associative.

The program must be run from the command line and requires Python 3.4+ to run. Executing the program will run the simulation and print an ASCII table containing the details for each supplied word address, as well as the final contents of the cache.

To see example input and output, see examples.txt.


You can install Cache Simulator via pip (ideally globally):

pip install cache-simulator

Command-line parameters

Required parameters


The size of the cache in words (recall that one word is four bytes in MIPS).


One or more word addresses (separated by spaces), where each word address is a base-10 positive integer.

Optional parameters


The program internally represents all cache schemes using a set associative cache. A value of 1 for this parameter (the default) implies a direct-mapped cache. A value other than 1 implies either a set associative or fully associative cache.


The number of words to store for each block in the cache; the default value is 1.


The number of bits used to represent each given word address; this value is reflected in the BinAddr column in the reference table. If omitted, the default value is the number of bits needed to represent the largest of the given word addresses.


The replacement policy to use for the cache. Accepted values are lru (Least Recently Used; the default) and mru (Most Recently Used).

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