chipleap 0.3.0

Tell it the model and the speed you need. ChipLeap designs the chip,
explains every choice, writes the RTL and checks it.

Website · Quick start · Docs · Changelog

_{A chip ChipLeap designed for SmolLM2 135M on the open IHP 130 nm PDK, rendered to scale from its floorplan.}

What it does

You describe a workload (say, Llama 3.2 1B decoding), a target (5 tokens per second) and your limits (area, power, process nodes). ChipLeap works out the rest:

1. Sizes the problem. The bandwidth, compute and memory the target needs, and which memories and nodes can deliver them.
2. Designs the architecture. An agent finds the bottleneck, tries every single change, keeps the best one and writes down why. It chooses the on-chip memory, the external memory, the dataflow, the array size, the precision, the CPU, the clock and the node.
3. Generates the hardware. Accelerator RTL in SystemVerilog, an X-HEEP RISC-V SoC configuration or AXI4 IP for any host, a C driver, a testbench and a datasheet.
4. Checks it. Simulation against a golden model, synthesis, place and route, and the SoC generator's own checks, on open-source tools or the commercial ones you already have.

_{The agent's decisions for Llama 3.2 1B at 5 tokens per second. Every floorplan is drawn to the same scale.}

Quick start

pip install chipleap                # or: uv tool install chipleap
chipleap init llama.yaml            # an example spec to edit
chipleap explore llama.yaml -o out  # decisions, Pareto front and the hardware in out/
chipleap verify out                 # simulate, synthesize and check it

Open out/report.html to see each decision, the Pareto front and where the time goes.

Ask your AI assistant

ChipLeap is also an MCP server, so Claude, Cursor, VS Code or Codex can drive it:

claude mcp add chipleap -s user -- chipleap mcp

Then ask things like "Design the smallest chip on the IHP open PDK that runs SmolLM2 135M at two tokens per second" or "Why is this design memory bound, and what is the cheapest fix?". docs/mcp.md covers the other clients.

Works with what you have

• Any workload: twelve LLM presets (SmolLM2, Qwen, Gemma, Llama, Phi, TinyLlama), or your own network of convolutions and matrix multiplies.
• Any host: a complete X-HEEP RISC-V SoC, or the accelerator alone as AXI4 IP for an Arm, RISC-V or FPGA SoC (platforms).
• Open tools: Verilator, Yosys and LibreLane (OpenROAD, KLayout, Netgen) on the IHP SG13G2 open PDK.
• Commercial tools: Cadence Xcelium and Genus, Synopsys VCS and Design Compiler, Siemens Questa, on your machine or on a design server over ssh (guide).
• Your own PDK: chipleap tech add measures it from its liberty files and keeps the numbers on your machine.

Every tool is optional. chipleap doctor lists what it found, and chipleap verify skips what is missing and says why.

Down to the layout

chipleap verify out --steps all adds place and route with LibreLane, the open flow Tiny Tapeout uses for its IHP shuttles. The picture is the GDS it wrote for the SmolLM2 chip's 1 x 8 GEMV engine: a 0.80 mm² core with clean DRC, LVS and antenna checks that meets its 90 MHz clock at the slow corner, with room to spare (about 101 MHz, and 148 MHz at the typical one).

The accelerator model is the same tile schedule the RTL runs, so it is checked against it:

• Cycles: equal to simulation without memory stalls, within a few percent with random stalls, on Verilator, Xcelium, VCS and Questa alike.
• Area: logic area within 3 % on average of synthesis on IHP SG13G2, across 12 configurations.
• Clock: the model allows what the routed accelerator meets at the slow corner: 100 MHz with one port, less with more ports or a wider GEMV engine.

The other nodes are scaled from published figures and say so. docs/model.md lists every number and its source; docs/verification.md explains each check.

Learn more

Contributing

Issues and pull requests are welcome; see CONTRIBUTING.md. pytest runs the suite, and the hardware tests run when their tools are installed.

License

MIT. Generated X-HEEP configurations carry X-HEEP's Apache-2.0 header. ChipLeap is an independent project, not affiliated with EPFL, IHP or any company named here.