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dau build

Build tools for dau

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Overview

dau-build turns declarative FPGA build specs into concrete artifacts: generated SystemVerilog, artlink.manifest/v0 artifact bundles, backend handoff manifests, Vivado Tcl, and ordered hardware command plans. Every operation is a typed ccflow.CallableModel composed from a Hydra config tree in dau_build/config, so the whole pipeline composes, inspects, and tests on a development machine, with the privileged steps (Vivado, JTAG, PCIe) gated behind an explicit execute=true.

Two synthesis engines are supported: Vivado (the FPGA bitstream flow) and yosys (open-source synthesis that runs in CI). The config plumbing is backend-agnostic, so more can be added.

Quickstart

Build the checked-in identity example — no board or vendor tools required:

dau-build task=tasks/spec/inspect  model.spec_path=examples/identity/dau-build.yaml
dau-build task=tasks/spec/build     model.spec_path=examples/identity/dau-build.yaml model.output_root=outputs/identity
dau-build task=tasks/spec/validate  model.manifest_path=outputs/identity/dau-identity.manifest model.root=outputs/identity
dau-build task=tasks/sim/simulate   model.module=dau_identity_top model.spec_path=examples/identity/dau-build.yaml

Task and step names are path-style, mirroring the config tree (task=tasks/spec/inspect, step=steps/inspect).

Documentation

The documentation is organized into four sections:

[!NOTE] This library was generated using copier from the Base Python Project Template repository.

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