Dataflow Compiler for Fast, Scalable Quantized Neural Network Inference on FPGAs

FINN+ is a fork of FINN, an experimental framework from the Integrated Communications and AI Lab of AMD Research & Advanced Development to explore deep neural network inference on FPGAs. It specifically targets quantized neural networks, with emphasis on generating dataflow-style architectures customized for each network. The resulting FPGA accelerators are highly efficient and can yield high throughput and low latency. The framework is fully open-source in order to give a higher degree of flexibility, and is intended to enable neural network research spanning several layers of the software/hardware abstraction stack.

Quick Links

• Getting Started - Start using FINN+ in minutes
• Wiki Documentation - Complete documentation and guides
• Feature Tracker - Current development status
• Contributing - Learn how to contribute to FINN+
• Citing FINN+ - How to cite FINN+ in your research
• Changelog - Recent additions and changes

What's New in FINN+

FINN+ incorporates all upstream FINN development while adding significant enhancements across multiple areas:

Core Improvements

• Transformer/Attention Support - Native support for modern transformer architectures
• Enhanced Streamlining - Improved optimization pipeline for better performance
• Smart FIFO Sizing - Automatic folding and FIFO-sizing with better algorithms
• QoR Estimation - Empirical quality-of-result estimation for design space exploration

Backend Extensions

• Hardware Profiling - Instrumentation for accurate performance measurement in simulation and hardware
• Alveo Support - Enhanced build flow for Xilinx Alveo cards
• Multi-FPGA - Support for distributed inference across multiple FPGAs
• Optimized Drivers - High-performance C++ drivers for better host-accelerator communication

Developer Experience

• Better Diagnostics - Improved logging and error handling throughout the framework
• Type Safety - Comprehensive type hinting and checking for better code quality
• YAML Configuration - Alternative YAML-based build configuration system
• Simplified Setup - Containerless installation and setup process

Track Development: Check our Feature Tracker for real-time status updates on all features. We merge improvements early to accelerate development and enable cutting-edge research.

Getting Started

This is a quick overview of how to get started, for additional information please refer to our Wiki!

Prerequisites

Before installing FINN+, ensure you have:

• Python: Version 3.11-3.14
• Xilinx Tools: Vivado, Vitis, and Vitis HLS (2022.2 or 2024.2)
• System Dependencies: See our dependency installation script for required packages

Installing via pip

After preparing the dependencies mentioned above, simply run the following to start a build flow:

# Make sure to create a fresh virtual environment for FINN+
pip install finn-plus                     # Install FINN+ and its Python dependencies via pip
finn deps update                          # Ensure FINN+ pulled all further dependencies (this might update packages in your venv!)
finn build build_config.yaml model.onnx   # Run a FINN+ build defined in a YAML file

For more detailed instructions, like installation for development use, please refer to our Wiki!

Contributing

Contributions are very welcome! Whether you are fixing a bug, adding a new feature, improving documentation, or sharing a model — every contribution helps.

To get started:

1. Fork the repository and create a feature branch from main.
2. Check the Feature Tracker to see what is planned or already in progress.
3. Open an issue to discuss larger changes before investing significant effort.
4. Submit a pull request with a clear description of your changes.

Please read CONTRIBUTING.md for detailed guidelines on code style, testing, and the review process.

Citing FINN+

If you find FINN+ useful in your research, please cite the Zenodo record using the following BibTeX entry:

@software{finn-plus,
  author       = {Jentzsch, Felix and Berganski, Christoph and Jungemann, Linus and Wintermann, Bjarne},
  title        = {{FINN+}},
  year         = {2026},
  publisher    = {Zenodo},
  doi          = {10.5281/zenodo.19100351},
  url          = {https://github.com/eki-project/finn-plus}
}

If you use a specific feature, please additionally cite the corresponding publication:

Multi-DNN: Jentzsch, Klassen et al., "Compiling Multi-DNN Dataflow Accelerators: Dynamic Weight Reconfiguration in FINN" (FPT '26 Poster)

Publication pending

Simulation-based FIFO-sizing: Jungemann, Wintermann et al., "Rapid Dataflow Buffer Sizing for DNNs via Parallel RTL Control-Path Simulation for FINN" (H2RC Workshop at SC '26)

Publication pending

LiveFIFO: Jentzsch et al., "LiveFIFO: FPGA-in-the-Loop Buffer Sizing for Dataflow Accelerators" (ARC '26)

@inproceedings{livefifo,
  author    = {Jentzsch, Felix and Preu{\ss}er, Thomas B. and Stasytis, Lukas and Umuro{\u{g}}lu, Yaman and Petri-Koenig, Jakoba and Berganski, Christoph and Platzner, Marco},
  title     = {{LiveFIFO}: {FPGA}-in-the-Loop Buffer Sizing for Dataflow Accelerators},
  booktitle = {Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC)},
  year      = {2027},
  pages     = {34--50},
  doi       = {10.1007/978-3-032-29365-7_3}
}

Empirical QoR Estimation: Jentzsch et al., "Empirical QoR Estimation Flow for Fast Design Space Exploration of DNN Dataflow Accelerators" (FPT '25 Poster)

@inproceedings{finn-qor,
  author    = {Jentzsch, Felix and Platzner, Marco},
  title     = {Empirical {QoR} Estimation Flow for Fast Design Space Exploration of {DNN} Dataflow Accelerators},
  booktitle = {International Conference on Field Programmable Technology (ICFPT)},
  year      = {2025},
  pages     = {231-232},
  doi       = {10.1109/ICFPT67023.2025.00044}
}

High-performance driver: Jungemann et al., "FINN-HPC: Closing the Gap for Energy-Efficient Neural Network Inference on FPGAs in HPC" (HEART '25)

@inproceedings{finn-hpc,
  author    = {Jungemann, Linus and Wintermann, Bjarne and Riebler, Heinrich and Plessl, Christian},
  title     = {{FINN-HPC}: Closing the Gap for Energy-Efficient Neural Network Inference on {FPGAs} in {HPC}},
  booktitle = {Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)},
  year      = {2025},
  pages     = {103--116},
  doi       = {10.1145/3728179.3728189}
}

Multi-FPGA: Pape, Wintermann et al., "AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference" (HEART '25)

@inproceedings{auroraflow,
  author    = {Pape, Gerrit and Wintermann, Bjarne and Jungemann, Linus and Lass, Michael and Meyer, Marius and Riebler, Heinrich and Plessl, Christian},
  title     = {{AuroraFlow}, an Easy-to-Use, Low-Latency {FPGA} Communication Solution Demonstrated on Multi-{FPGA} Neural Network Inference},
  booktitle = {Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)},
  year      = {2025},
  pages     = {35--48},
  doi       = {10.1145/3728179.3728190}
}

Transformer support: Berganski et al., "FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers" (FPT '24)

@inproceedings{finn-t,
  author    = {Berganski, Christoph and Jentzsch, Felix and Platzner, Marco and Kuhmichel, Max and Giefers, Heiner},
  title     = {{FINN-T}: Compiling Custom Dataflow Accelerators for Quantized Transformers},
  booktitle = {International Conference on Field Programmable Technology (ICFPT)},
  year      = {2024},
  pages     = {1--10},
  doi       = {10.1109/ICFPT64416.2024.11113391}
}

About Us

FINN+ is maintained by researchers from the Computer Engineering Group (CEG) and Paderborn Center for Parallel Computing (PC²) at Paderborn University, Germany as part of the eki research project.