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Easy-To-Use SystemVerilog Parser

Features

  • Extract Port Lists
  • Extract Parameters
  • Extract Submodule Instances and their connections
  • ifdef support
  • Standards: IEEE 1800-2009 SystemVerilog

Limitations

  • No Syntax Checks - Source Code files must be syntactically correct
  • No Full Parser - This parser intends to be simple and just extract some information from the source code. Fast and Simple.

Installation

Installing it is pretty easy:

pip install hdl-parser

Authors

Usage

See Usage Documentation

Project links

Data verified by PyPI on Dec 4, 2025
Data provided by the project maintainers, verified at the time the release was uploaded to PyPI.

Key dates

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  • Released:
Latest release

1 maintainer

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Avatar for emacedo from gravatar.com emacedo

Credits

Author: Eric Macedo

GitHub Statistics

Data verified by PyPI on Dec 4, 2025
The GitHub source repository was provided by the project maintainers and verified by PyPI at the time of upload. Stars, forks, and open issues/PRs are derived from that repository and have not been independently verified.

Requires

Python <4.0, >=3.10.0

Tags

SystemVerilog Verilog Parser

Classifiers

Report project as malware

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This release

1.1.0 This release

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1.0.1

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1.0.0

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0.6.1

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