hectare 0.2.4

VHDL generator from SystemRDL

HECTARE - Hamburg Elegant CreaTor from Accellera™ systemrdl™ to REgisters

This is a tool which generates AXI4-Lite slave from a description in SystemRDL.

It uses systemrdl-compiler as a front end and a custom backend to generate a VHDL module.

The HECTARE tool is developed by MicroTCA Tech Lab at DESY.

Usage

$ hectare.py --help
usage: hectare.py [-h] [--debug] [--axi-vhdl VHDL_NAME] filename

HECTARE - Hamburg Elegant CreaTor from Accelera systemrdl to REgisters

positional arguments:
  filename              .rdl file

optional arguments:
  -h, --help            show this help message and exit
  --debug               enable debugging information
  --axi-vhdl VHDL_NAME  generate AXI4-Lite slave

Useful arguments

• sw: r, rw, w, na
• hw: r, rw, w, na
• swmod
• singlepulse
• woclr
• encode

Changelog

[0.2.4] - 2021-06-19

• Read decode error returns 0xbadcofee

[0.2.3] - 2021-06-07

• Add support for woclr

[0.2.2] - 2021-04-11

• Add support for singlepulse

[0.2.1] - 2021-02-19

• Add C header generator
• Add support for reset values
• Add version argument (--version) to print version information

[0.2.0] - 2020-06-08

• First public release
• Provides generation of AXI4-Lite module in VHDL
• Supports all possible combination for sw and rw properties as well as swmod and encode attribute

Tests

Several tests are provided in test folder

00_unit_test

This is a simple unit test based on the Python [] framework.

01_uvvm_simple

UVVM version: v2019.12.04

Regenerating the output products (in shell, from folder hdl):

$ ./gen_output.sh
Parsing finished.
generate_package
Generating mymodule.vhd ...
Generating mymodule_pkg.vhd ...
Done.

Running the test (in ModelSim, from folder work)

do ../scripts/compile_uvvm.do
do ../scripts/sim.do

02_hdlparse

Requires hdlparse from a fork (the one from pip is missing some features) available from https://github.com/andresmanelli/hdlparse on branch entity.

03_ordt_equivalence

Compares the output of HECTARE against Juniper® ordt.

Alias to ordt should be created, as explained here.

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Accellera™ and SystemRDL™ are trademarks of Accellera Systems Initiative Inc.

Juniper® is a registered trademark of Juniper Networks, Inc.