HGDB RTL
This is an experimental tool to generate symbol table from SystemVerilog designs. It uses slang as a frontend to parse any SystemVerilog files.
How to install
TO install, simply run the following commands
pip install hgdb-rtl
hgdb-rtl will show up in your path.
Limitations
Since SystemVerilog is a complex language, there are several limitation in the current implementation. Notice that none of them are systematic - given enough engineering effort, they can be overcome.
- No SSA transformation for
always_comblogic. This means that if you reassign the same variable in the samealways_combblock, the intermediate result will not show in during debugging. - Local variables declared in the procedural will not be detected.
Metadata
Release files for hgdb-rtl 0.0.1
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Built distribution (wheel)
| File | Interpreter | ABI | Platform | Reset |
|---|---|---|---|---|
| hgdb_rtl-0.0.1-py3-none-manylinux_2_17_x86_64.manylinux2014_x86_64.whl | Python 3 | none | Linux glibc 2.17+ x86-64 | Details |
Release files / hgdb_rtl-0.0.1-py3-none-manylinux_2_17_x86_64.manylinux2014_x86_64.whl
| Download URL | hgdb_rtl-0.0.1-py3-none-manylinux_2_17_x86_64.manylinux2014_x86_64.whl |
|---|---|
| Size | 2.0 MB |
| Tags | Linux glibc 2.17+ x86-64 Python 3 |
|
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8cfb5a63d29ede27a4ff7ecba25dadbf017104def8ef6bb754e150a16a367277
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twine/4.0.1 CPython/3.11.0
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Security for hgdb-rtl 0.0.1
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