Lambdapdk
Lambdapdk is a collection of open-source Process Design Kits (PDKs) that enable chip design across multiple technology nodes. Each PDK includes standard cell libraries, I/O libraries, and memory compilers with full integration into the SiliconCompiler build system and Lambdalib Verilog hardware abstraction library.
Why Lambdapdk?
Challenges
- PDK setup is complex and error-prone
- Technology-specific designs limit portability
- Commercial PDKs have restrictive licenses
- Scattered PDK sources with inconsistent interfaces
Solution
- Pre-configured PDKs ready for immediate use
- Lambdalib mapping enables design portability
- Fully open-source PDKs for research and education
- Unified API across all supported technologies
Supported PDKs
| PDK | Node | Libraries | Source |
|---|---|---|---|
| GT2N | 2nm GAAFET | Standard cells (HVT/SVT/LVT/ULVT/ELVT) | Georgia Institute of Technology |
| ASAP7 | 7nm FinFET | Standard cells (RVT/LVT/SLVT), I/O, SRAM | Arizona State University |
| FreePDK45 | 45nm | Nangate standard cells, SRAM | NC State / Nangate |
| ICsprout55 | 55nm | Standard cells (HVT/RVT/LVT) | ICsprout / ECOS |
| Sky130 | 130nm | Standard cells (HD/HDLL), I/O, SRAM | Google / Skywater |
| GF180 | 180nm | Standard cells (7T/9T), I/O, SRAM | Google / GlobalFoundries |
| IHP130 | 130nm SiGe | Standard cells, I/O, SRAM | IHP GmbH |
| Interposer | Multi-layer | Bump cells for chiplet integration | ZeroASIC |
Quick Start
Installation
pip install lambdapdk
Basic Usage
from siliconcompiler import ASIC, Design
from siliconcompiler.targets import skywater130_demo
# Create design and add source files
design = Design("mydesign")
design.set_topmodule("mydesign", fileset="rtl")
design.add_file("mydesign.v", fileset="rtl")
design.add_file("mydesign.sdc", fileset="sdc")
# Create ASIC project and load target
project = ASIC(design)
project.add_fileset(["rtl", "sdc"])
skywater130_demo(project)
# Run the flow
project.run()
project.summary()
Available targets: asap7_demo, freepdk45_demo, skywater130_demo, gf180_demo, ihp130_demo, interposer_demo, gt2n_demo, and icsprout55_demo.
Cell Library Inventory
GT2N (2nm)
Ten standard cell libraries covering two nanosheet width flavors and five threshold voltages:
| Library | Nanosheet width | Vt flavors | Cells |
|---|---|---|---|
| gt2_6t_w13_* | 13nm | HVT, SVT, LVT, ULVT, ELVT | 72 each |
| gt2_6t_w31_* | 31nm | HVT, SVT, LVT, ULVT, ELVT | 72 each |
Python classes follow the pattern GT2N6TW<width><vt>, e.g. GT2N6TW31SVT (the gt2n_demo main library).
Cell categories: AND, OR, NAND, NOR, XOR, XNOR, INV, BUF, MUX, DFF (async reset), AO, AOI, OA, OAI, Tie, Filler, Decap, Tap
Note: GT2N is backside-power-delivery (BSPDN); the libraries use the backside tap cell variant. Cell views are downloaded from the upstream GT2N repository; this package provides the technology setup and APR scripts.
ASAP7 (7nm)
Standard cell libraries with three threshold voltage variants:
| Library | Type | Cells | Verilog |
|---|---|---|---|
| asap7sc7p5t_rvt | Regular Vt | ~200 | verilog |
| asap7sc7p5t_lvt | Low Vt | ~200 | verilog |
| asap7sc7p5t_slvt | Super Low Vt | ~200 | verilog |
Cell categories: AND, OR, NAND, NOR, XOR, INV, BUF, MUX, DFF, Latch, Adder, Tie, Filler, Decap, Tap
Memory macros (fakeram7):
| Configuration | Verilog |
|---|---|
| Single-port 64x32 to 8192x64 | verilog |
| Dual-port 64x32 to 8192x64 | verilog |
| True dual-port 64x32 to 8192x64 | verilog |
FreePDK45 (45nm)
| Library | Type | Verilog |
|---|---|---|
| nangate45 | Standard cells | lambda |
Cell categories: AND, OR, NAND, NOR, XOR, INV, BUF, MUX, DFF, Latch, AOI, OAI, Tie, Filler, Tap
Memory macros (fakeram45):
| Configuration | Verilog |
|---|---|
| 64x32 to 512x64 | verilog |
ICsprout55 (55nm)
Three threshold-voltage variants of the same 7-track library, on a 1.4um core7 site:
| Library | Type | Cells |
|---|---|---|
| ics55_stdcell_h | High Vt | 747 |
| ics55_stdcell_r | Regular Vt | 747 |
| ics55_stdcell_l | Low Vt | 747 |
Cell categories: AND, OR, NAND, NOR, XOR, XNOR, INV, BUF, Tristate, MUX, DFF, Scan DFF, Latch, AOI, OAI, ICG, Delay, Adder, Tie, Filler, Decap, Tap, Antenna
Nothing from ICsprout55 is vendored here: LEF, CDL and Verilog are fetched from the upstream repository archive, and liberty and GDS from the matching release assets. See the PDK README for the collateral that lambdapdk supplies itself, and for the gaps (no DRC/LVS decks, no SRAM, no I/O yet).
Sky130 (130nm)
| Library | Type | Cells | Verilog |
|---|---|---|---|
| sky130hd | High Density | ~430 unique | verilog |
| sky130hdll | High Density Low Leakage | ~140 unique | verilog |
| sky130io | I/O cells | Various | verilog |
Cell categories: AND, OR, NAND, NOR, XOR, INV, BUF, MUX, DFF, Latch, AOI, OAI, Delay, Tie, Filler, Decap, Tap, Antenna
Memory macros (sky130sram):
| Configuration | Verilog |
|---|---|
| 1RW1R 64x256 | verilog |
GF180 (180nm)
| Library | Type | Cells | Verilog |
|---|---|---|---|
| gf180mcu_fd_sc_mcu7t5v0 | 7-track | ~230 | verilog |
| gf180mcu_fd_sc_mcu9t5v0 | 9-track | ~230 | verilog |
| gf180mcu_fd_io | I/O cells | Various | verilog |
Cell categories: AND, OR, NAND, NOR, XOR, INV, BUF, MUX, DFF, Latch, AOI, OAI, Tristate, Delay, Tie, Filler, Decap, Tap, Antenna
Memory macros (gf180sram):
| Configuration | Verilog |
|---|---|
| 64x8 to 512x8 | verilog |
IHP130 (130nm SiGe)
| Library | Type | Verilog |
|---|---|---|
| sg13g2_stdcell | Standard cells | lambda |
| sg13g2_io | I/O cells | blackbox |
Note: IHP130 cell views are provided by the IHP Open PDK.
Interposer
| Library | Type | Description |
|---|---|---|
| bumps | Bump cells | Micro-bump cells for chiplet integration |
Stackup variants: 3ML, 4ML, 5ML with 400um, 800um, and 2000um bump pitches.
Architecture
lambdapdk/
├── gt2n/ # 2nm GAAFET PDK
│ ├── base/ # Technology files
│ └── libs/ # Standard cells
├── asap7/ # 7nm FinFET PDK
│ ├── base/ # Technology files, DRC rules
│ └── libs/ # Standard cells, I/O, memory
├── freepdk45/ # 45nm PDK
│ ├── base/
│ └── libs/
├── icsprout55/ # 55nm PDK
│ ├── base/
│ └── libs/
├── sky130/ # 130nm PDK
│ ├── base/
│ └── libs/
├── gf180/ # 180nm PDK
│ ├── base/
│ └── libs/
├── ihp130/ # 130nm SiGe PDK
│ ├── base/
│ └── libs/
└── interposer/ # Passive interposer
├── base/
└── libs/
Contributing
We welcome contributions! Please report issues and submit pull requests at: https://github.com/siliconcompiler/lambdapdk/issues
License
This project is licensed under the Apache License 2.0.
Individual PDKs may have additional license terms:
| PDK | License | Details |
|---|---|---|
| ASAP7 | BSD 3-Clause | LICENSE |
| Nangate45 | Nangate Open Cell Library License | LICENSE (non-commercial use) |
| Sky130 | Apache 2.0 | Via open_pdks |
| GF180 | Apache 2.0 | Via gf180mcu-pdk |
| IHP130 | Apache 2.0 | Via IHP-Open-PDK |
| Interposer | Apache 2.0 | Copyright 2024 ZeroASIC Corp |
Copyright 2023 Zero ASIC Corporation
Release files for lambdapdk 0.2.20
For a detailed explanation of source distributions (sdists) and built distributions (wheels), please see the package formats documentation.
Source distribution (sdist)
| File | Size | Uploaded | |
|---|---|---|---|
| lambdapdk-0.2.20.tar.gz | 69.4 kB | Details |
Built distribution (wheel)
| File | Interpreter | ABI | Platform | Reset |
|---|---|---|---|---|
| lambdapdk-0.2.20-py3-none-any.whl | Python 3 | none | any | Details |
Total release size: 140.6 kB
Release files / lambdapdk-0.2.20.tar.gz
| Download URL | lambdapdk-0.2.20.tar.gz |
|---|---|
| Size | 69.4 kB |
| Tags | Source |
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