llnn 0.1.4

LLNN: A Scalable LUT-Based Logic Neural Network Architecture for FPGAs

LLNN: A Scalable LUT-Based Logic Neural Network Architecture for FPGAs

This repository implements Look-Up Tables Logic Neural Networks (LLNNs) presented in:

LLNN: A Scalable LUT-Based Logic Neural Network Architecture for FPGAs

📖 Citing

If you use this work, please cite the following paper:

@ARTICLE{11154450,
  author={Ramírez, Iván and Garcia-Espinosa, Francisco J. and Concha, David and Aranda, Luis Alberto and Schiavi, Emanuele},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers}, 
  title={LLNN: A Scalable LUT-Based Logic Neural Network Architecture for FPGAs}, 
  year={2025},
  volume={},
  number={},
  pages={1-13},
  keywords={Logic gates;Field programmable gate arrays;Biological neural networks;Table lookup;Hardware;Computer architecture;Training;Neurons;Logic;Complexity theory;Logic neural networks;LUT-based neural networks;FPGA implementation;scalability in hardware neural networks;real-time inference},
  doi={10.1109/TCSI.2025.3606054}
}

Installation

pip install llnn

Importing LUTLayer

import torch
from llnn.lutlayer import LUTLayer, Aggregation

model = torch.nn.Sequential(
    torch.nn.Flatten(),
    LUTLayer(input_dim=1000, lut_size=6, n_luts=2048),
    LUTLayer(input_dim=2048, lut_size=6, n_luts=4000),
    Aggregation(num_classes=10, tau=10)
)

Train a model

python main.py --train --save --name model1 --dataset mnist --batch-size 128 -lr 0.01 --num-iterations 10000

Test a trained model

python main.py --load --name model1 --dataset mnist

VHDL

HDL code generation example

python hdl/vhdl/convert2vhdl.py --model model1

LLNN Testbench

We offer a testbench in VHDL code to test a trained MNIST network and additional utility functions to convert the MNIST dataset into binary inputs for hardware validation in simulation.