Luxtelligence Process Design Kit (PDK) for gdsfactory

Luxtelligence's PDK is built on a lithium tantalate/lithium niobate electro-optic platform, leveraging their large Pockels coefficients for high-speed modulation.

Luxtelligence Process Design Kit (PDK) for gdsfactory. The Luxtelligence PDK contains a library of components that facilitate the design of photonic integrated circuits for Luxtelligence's foundry service. The PDK includes both electrical and optical building blocks that leverage Lithium Tantalate and Lithium Niobate's electro-optic effect and attractive optical properties. Each building block consists of a geometrical layout, defining the starting point for microfabrication of the integrated circuit, and a compact circuit model that approximates the real frequency-domain behaviour of the component.

The lxt_pdk_gf PDK is released open-source to allow users to easily evaluate a sample of what Luxtelligence has to offer. Please contact us for information on advanced building blocks and variations on the standard PDK geometry.

Installation

We recommend KLayout as a layout viewer and editor for GDS and OASIS files. gdsfactory itself is based on and closely integrated with KLayout.

Python 3.12 is required. We recommend VSCode or Google Antigravity as IDEs.

If you do not have Python installed, you can download Anaconda. Once Python is available, clone the repository and install the package in editable mode:

git clone https://github.com/Luxtelligence/lxt_pdk_gf.git
cd lxt_pdk_gf
pip install -e .
python install_tech.py

Restart KLayout afterwards to ensure the newly installed technology appears.

KLayout Layer Properties

Each PDK has a klayout/ folder containing .lyp layer property files (e.g. ltoi300/klayout/ and lnoi400/klayout/). These files define the colours, fill patterns, and display names for every process layer.

To activate them in KLayout:

1. Open KLayout and go to File → Setup.
2. Navigate to the Application section and select Layer Properties.
3. Under Default layer properties file, click Browse and point it to the .lyp file for your PDK (e.g. lxt_pdk_gf/ltoi300/klayout/ltoi300.lyp).
4. Click Apply and OK. Restart KLayout to apply the changes.

KLayout DRC

Design Rule Check (DRC) runsets for KLayout can be downloaded from resources.luxtelligence.ai. The files have a .lydrc extension and are specific to the technology stack you are using.

Installation:

Place the downloaded .lydrc file(s) in your local KLayout DRC folder:

<user home folder>/Klayout/drc/

Note: KLayout has a known issue where only the first DRC file in the drc/ folder is actually used. It is recommended to keep only one .lydrc file in that folder at a time. If you need to switch between DRC scripts for different stacks, simply replace the file.

Running the DRC in KLayout:

1. Open your GDS layout in KLayout.
2. Go to Tools → DRC.
3. Click Edit DRC Script and select the .lydrc file corresponding to your process stack.
4. Run the script. The results will appear in a dedicated DRC results window, where violations are listed and can be highlighted in the layout.

Important: Not every flagged violation necessarily needs to be corrected — some rules may be advisory or context-dependent. Conversely, the DRC script does not guarantee that all possible design errors are caught. Always review results in the context of your specific design intent and consult Luxtelligence if in doubt.

Examples

Chip edge, singulation, and polishing

For LNOI400 edge couplers, the outside edge of layer 6/1 (CHIP_EXCLUSION_ZONE) is the physical chip edge. Layer 6/0 (CHIP_CONTOUR) serves other layout purposes and does not define the straight tip extension.

The coupler tip extends 5 µm outside layer 6/1, regardless of the total straight tip length. At least 5 µm of constant-width straight remains inside that edge for successful singulation:

Process	Total straight tip (input_ext)	Outside 6/1	Inside 6/1
Singulation without polishing	10 µm	5 µm	5 µm
Singulation with polishing allowance	Approximately 30 µm	5 µm	Approximately 25 µm

The longer polishing option keeps the width at the polished facet constant. Do not use the longer straight by default when polishing is not planned: the large tip mode interacts with silicon over a longer distance, which can increase edge-coupler insertion loss. The required polishing allowance depends on the planned process; approximately 30 µm is a guide, not a predicted loss or a fixed polishing removal depth.

lnoi400.cells.die_phix_rf() uses the standard LXT chip frame and the 10 µm straight tip by default. For polishing, keep the same 5 µm facet offset and change only the straight length:

import lnoi400
from lnoi400 import cells

lnoi400.PDK.activate()
die = cells.die_phix_rf(
    edge_coupler={
        "component": "double_linear_inverse_taper_mirror",
        "settings": {"input_ext": 30.0},
    },
    fiber_coupler_xoffset=5.0,
)

Both right and optional left coupler arrays use this outward offset from 6/1. Custom couplers must supply at least 10 µm of constant-width straight tip. The low-level unmirrored double_linear_inverse_taper retains its zero-extension default; set input_ext explicitly when using it at a singulated chip edge.

The die wrapper follows chip_frame dimension restrictions: nominal dimensions of 5000, 10000, and 20000 µm map to layer-6/0 extents of 4950, 10000, and 20100 µm respectively, within the frame's existing tolerances. A nominal 5000-by-5000 µm die is unsupported. Layer 6/1 adds exclusion_zone_width on each side. Pad offsets remain referenced to layer 6/0.

After installing the PDK, you can verify that it is working correctly by running the Jupyter notebooks in the docs/notebooks folder.

Documentation

• PDK documentation
• gdsfactory documentation

Pre-commit

Pre-commit hooks are centrally maintained in pdk-ci-workflow-public. make dev fetches the canonical config and installs the git hook.

make dev

Tests

Run the test suite:

make test

Release

1. Bump the version:

tbump 0.0.1

2. Push the tag:

git push --tags

This triggers the release workflow that builds wheels and uploads them.

3. Create a pull request with the updated changelog since last release.