najaeda 0.7.4

Naja EDA Python package

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najaeda is a Python package for working with gate-level netlists — load, navigate, edit, and analyse designs from simple Verilog files to large SystemVerilog cores.

from najaeda import netlist

# Load a gate-level Verilog design with a Liberty standard-cell library
netlist.load_liberty(['NangateOpenCellLibrary.lib'])
top = netlist.load_verilog('my_design.v')

# Navigate the hierarchy
for inst in top.get_child_instances():
    print(f'{inst.get_name()} → {inst.get_model_name()}')

# Flat connectivity across hierarchy boundaries
for iterm in top.get_term('clk').get_equipotential().get_inst_terms():
    print(iterm)

# Edit: rename, reconnect, delete
top.get_net('old_name').set_name('new_name')

What you can do

• Load structural Verilog and SystemVerilog designs, with or without Liberty standard-cell libraries

• Navigate hierarchy, nets, and ports at any level of detail — instance-by-instance or flat via equipotentials

• Edit netlists: rename instances and nets, disconnect and reconnect signals, delete logic

• Analyse designs with the visitor API and export results to pandas for further processing or visualisation

Installation

pip install najaeda

Requires Python 3.8+. Wheels are published for Linux, macOS, and Windows.

Tutorials

Six hands-on notebooks — open any of them in Google Colab with no local install needed:

#	Topic	Colab
1	Getting started — load Verilog, navigate hierarchy, visualize
2	Liberty primitives — load a synthesised design with standard cells
3	Editing a netlist — rename, disconnect, reconnect, delete
4	SystemVerilog elaboration — load and browse an elaborated SV design
5	ibex RISC-V core — explore a real-world SV core, collect module stats
6	Fanout analysis — compute fanout for every net, trace drivers, export to pandas

Links

• API documentation

• GitHub repository

• Issue tracker

• Matrix chat

• [e-mail]

License

Apache License 2.0. See the LICENSE file for details.