neuralecosystems 4.10.0

Full-stack AI development ecosystem: DSL transpiler, 6-backend GPU cascade, custom RISC-V, 19 pillars

NeuralEcosystems

A full-stack AI development ecosystem spanning custom silicon through intelligent deployment. Single source, five deployment targets.

What it does

NeuralEcosystems is a domain-specific language (DSL) and transpiler system that lets you write AI models once in NeuralScript and deploy to any compute backend — CUDA, ROCm, MPS, XPU, DirectML, or CPU — without code changes. The ecosystem integrates KV-cache compression at the DSL level, custom RISC-V processor instructions for sparse operations, and a 19-pillar architecture covering everything from radio transport to fuzzy control.

model ResNet:
    layers: [Conv2D(3, 64), BatchNorm(), ReLU()]
    precision: int4
    kv_cache: compress=True, ratio=3.7

    deploy:
        device: "auto"
        pipeline: model >> quantize >> fuse >> export

This compiles to optimized Python, dispatches to the best available GPU backend, applies INT4 quantization with outlier-aware KV-cache compression, and exports to ONNX/TFLite/RISC-V binary — all from 8 lines of .ns source.

Architecture

19 pillars, organized into 9 dependency-ordered gates:

Gate	Pillars	Layer
G1	NeuralOS	Runtime kernel — config, process, resource, event, security
G2	NeuralScript, NeuralScript++	Two-layer language: DSL transpiler + Python superset
G3	NeuralCPU, NeuralGPU, NeuralFuse	Compute backends + sparse-quantized fusion engine
G4	NeuralRV, NeuralEdge	Custom RISC-V SoC + edge deployment profiles
G5	NeuralDB, NeuralPipe	Data layer — query DSL, model>>pipeline syntax
G6	NeuralSense, NeuralAuto, NeuralFuzzy	Intelligence — simulation, AutoML, fuzzy control
G7	NeuralIP, NeuralSDR, NeuralMesh	Communication — 30 transports, radio mesh, routing
G8	NeuralUI, NeuralZone, NeuralGuard	Interface + security — bindings, zones, encryption
P9	14 cross-pillar bridges	Wires the ecosystem into a connected graph

See ARCHITECTURE.md for the full bridge map and design rationale.

Key capabilities

6-backend GPU cascade — Automatically detects and dispatches to the best available compute backend: CUDA → ROCm → MPS → XPU → DirectML → CPU. Write once, run on NVIDIA, AMD, Apple Silicon, Intel, or any CPU.

KV-cache compression at DSL level — The kv_cache: block integrates INT4 quantization with outlier-aware compression directly in the language. 3.7x compression ratio validated across sequence lengths 128–4096 tokens, hardware-independent.

Custom RISC-V instructions — 21 custom opcodes including QPACK/QUNPK for quantized packing and 5 sparse operations (SPGEMM, MQNT, FUSE, SPRUNE, SPDOT) compiled from NeuralScript source through a complete .ns → compiler → assembler → SoC pipeline.

NeuralScript++ — Python superset with pipe operator (>>), null coalescing (??), optional chaining (?.), guard clauses, 25 domain shorthand libraries, and 277 shorthand methods. 2.5x code reduction over standard Python. Transpiles to standard Python in 3 passes.

14 cross-pillar bridges — Each bridge connects exactly two pillars with a concrete operation. Bridge chains enable multi-hop workflows: compile → encrypt → route → decrypt across 4 pillars in a single validated call.

Installation

pip install neuralecosystems

Requires Python 3.10+. No external dependencies for core functionality.

Quick start

# Run the full test suite (1,352 tests)
py run_all_tests.py

# Bridge self-test (48 checks)
py ns_bridges.py

# Bridge + integration tests via pytest (173 tests)
py -m pytest test_ns_bridges.py test_v4_integration.py -v

# 20-dimension ecosystem audit
py v4_ecosystem_audit.py

Project structure

NeuralEcosystems/
├── neural_os/          # G1: Runtime kernel (10 files, 2487 lines)
├── neural_script/      # G2: DSL transpiler (4 files, 975 lines)
├── neural_script_pp/   # G2: Python superset (4 files, 1109 lines)
├── neural_cpu/         # G3: CPU compute backend
├── neural_gpu/         # G3: GPU 6-backend cascade
├── neural_fuse/        # G3: Sparse-quantized fusion
├── neural_rv/          # G4: Custom RISC-V SoC (743 lines)
├── neural_edge/        # G4: Edge deployment profiles
├── neural_db/          # G5: Query DSL + in-memory engine
├── neural_pipe/        # G5: Pipeline operator (model >> stage)
├── neural_sense/       # G6: Simulation engine
├── neural_auto/        # G6: AutoML hyperparameter search
├── neural_fuzzy/       # G6: Mamdani fuzzy controllers
├── neural_ip/          # G7: 30-transport protocol layer
├── neural_sdr/         # G7: Software-defined radio
├── neural_mesh/        # G7: Mesh topology + routing
├── neural_ui/          # G8: Bidirectional UI bindings
├── neural_zone/        # G8: Security zones + policies
├── neural_guard/       # G8: Encryption + threat detection
├── ns_bridges.py       # P9: 14 cross-pillar bridges
├── tests/              # Gate test suites (1,144 tests)
├── test_ns_bridges.py  # Bridge unit tests (173 tests)
├── test_v4_integration.py  # Integration tests (31 tests)
└── v4_ecosystem_audit.py   # 20-dimension audit scanner

Test counts

Suite	Tests	Coverage
Gate 1: NeuralOS	198	Runtime kernel, config, security
Gate 2: Language	189	Parser, transpiler, NS++ syntax
Gate 3: Compute	142	CPU, GPU cascade, fuse engine
Gate 4: Silicon	133	RISC-V pipeline, edge profiles
Gate 5: Data	105	DB queries, pipeline operator
Gate 6: Intelligence	110	Simulation, AutoML, fuzzy
Gate 7: Communication	117	30 transports, mesh routing
Gate 8: UI+Zone+Guard	150	Bindings, zones, encryption
P9 Bridge self-test	48	All 14 bridges + health/lazy/chain
P9 pytest	173	Unit + cross-bridge integration
Total	1,365

IP protection

All code runs 100% locally. The runtime enforces:

• runtime.local_only — locked at boot, cannot be disabled
• runtime.no_telemetry — no telemetry, analytics, or tracking
• runtime.no_internet — no external network calls
• security.ip_protection — all 19 pillars IP-protected at boot

External network calls are permanently blocked even with Permission.ALL.

Patent

USPTO Application #64/018,500 filed March 27, 2026.

Title: Multi-Layer Domain-Specific Language Transpiler System with Integrated Memory Compression Directives and Custom Processor Instruction Set Extensions

License

Proprietary. All rights reserved. Contact [e-mail] for licensing.

Author

Sulthan Saleem Yahub — Dubai, UAE