nxpu 0.4.0

NXPU NeuroSymbolic Processing Unit SDK — AI that discovers rules from data, no LLM, no training

NXPU -- NeuroSymbolic Processing Unit

The AI chip that reasons instead of guessing. Zero training. Zero hallucination. 78x lower energy than Intel Core Ultra 9. Silicon-validated on FPGA.

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What is NXPU?

NXPU is a purpose-built reasoning processor that performs logical inference at hardware speed. Unlike GPUs (optimized for matrix math) or LLMs (statistical pattern matching), NXPU executes deterministic Datalog inference with variable binding, rule chaining, and backtracking -- directly in silicon.

LLMs guess with 80% confidence. NXPU proves with 100% certainty.

# NXLang -- the NXPU programming language
fact: patient_takes(john, warfarin).
fact: patient_takes(john, fluconazole).
fact: drug_metabolized_by(warfarin, CYP2C9).
fact: inhibits(fluconazole, CYP2C9).
fact: narrow_therapeutic(warfarin).

rule: concentration_risk(Patient, Drug, Inhibitor) :-
    patient_takes(Patient, Drug, _),
    drug_metabolized_by(Drug, Enzyme, _),
    inhibits(Inhibitor, Enzyme, _),
    patient_takes(Patient, Inhibitor, _).

rule: adverse_interaction(Patient, Drug) :-
    concentration_risk(Patient, Drug, _),
    narrow_therapeutic(Drug, _, _).

# NXPU derives: adverse_interaction(john, warfarin)
# "John's warfarin concentration is dangerously elevated by fluconazole"
# 164 clock cycles. 1.64 microseconds. Zero training. 100% correct.

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Silicon-Validated Performance

All measurements from ZCU106 FPGA (xczu7ev), April 2026. Not simulation -- real silicon.

Metric	NXPU (FPGA)	Python 3.14 (Intel Core Ultra 9 285)	GPU (H100 LLM)
Query latency	10 ns (1 cycle)	370 ns	~500 ms
Derivation (3 rules, 5 facts)	1.65 us	6.40 us (50K iter median)	N/A
Energy per derivation	1.65 uJ	~128 uJ (est. 20W x 6.4us)	~390,000 uJ/token
Accuracy on logic	100%	100%	80-90% (hallucinates)
Training required	None	None	~1,300 MWh
Throughput (native)	100M queries/sec	--	--
Reasoning throughput	2.3M derives/sec	--	--

Benchmark Results (All on Silicon)

Benchmark	Domain	Facts	Rules	Derived	Cycles	Accuracy
Security threat detection	Cybersecurity	12	3	5	165	100%
Drug interaction (pharma)	Healthcare	15	2 (4-body)	4	164	100%
Math technique selection	Education	24	10	12	214	100%
Dependency vulnerability	DevSecOps	8	3	4	184	100%
RBAC access control	IAM/Zero Trust	9	2	5	107	100%
GDPR compliance	Legal/Privacy	12	2	3	141	100%
Clinical compound risk	Healthcare	11	3	3	275	100%
Supply chain disruption	Economics	8	2	4	116	100%
Ecological food chain	Biology	7	1	4	72	100%
Transitive reachability	Graph theory	4	1	3	57	100%
100-rule stress test	Scale test	50	100	--	4,400	100%
Code synthesis	Programming	10	3	9	~60	100%

Total: 12 benchmarks, 10 domains, 0 failures, 0 false positives.

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9 Silicon-Validated Capabilities

#	Capability	What It Proves
1	O(1) Parallel Fact Search (CAM-256)	10ns query across 256 entries simultaneously
2	Datalog Forward-Chaining (rule_eval)	Variable binding, backtracking, dedup, rule chaining
3	Spiking Neural Network (16 LIF + STDP)	Online learning without backpropagation
4	Autonomous Concept Formation	Zero-shot learning from observation (no training)
5	NLU Text Pipeline	ASCII text -> structured facts -> reasoning
6	Neurosymbolic Feedback Loop	Neural perception <-> symbolic reasoning on one chip
7	Self-Modifying Rules	Chip tracks rule performance, promotes/demotes/deletes
8	Cross-Domain Analogy	Transfer reasoning patterns across domains (255/255 match)
9	Hardware Cycle Counter	Clock-accurate performance measurement

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NXLang Compiler & SDK

NXPU ships with a complete compiler toolchain: NXLang source -> NXIR -> Hardware registers -> Silicon.

Language (NXLang v0.3)

# Facts: ground truth
fact: vulnerable(CVE_2024_1234, openssl, v3_0_1).
fact: runs_service(web_01, openssl, v3_0_1).

# Rules: logical inference
rule: at_risk(Server) :-
    runs_service(Server, S, V),
    vulnerable(_, S, V),
    internet_facing(Server, _, _).

# Queries
query: at_risk.

Compiler (nxc)

# Compile to hardware format
nxc hw-compile program.nx --format tcl     # Vivado Tcl script
nxc hw-compile program.nx --format nxb     # Binary (deploy anywhere)
nxc hw-compile program.nx --format json    # Human-readable
nxc hw-compile program.nx --format c       # C header array

# Deploy to FPGA
nxc deploy program.nxb --transport jtag

# Interactive REPL
nxc repl --transport sim

Python SDK

import nxpu

# Connect to hardware (or "sim" for software simulation)
session = nxpu.connect("jtag", host="192.168.0.142")

# Add knowledge
session.add_fact("patient_takes", "john", "warfarin")
session.add_fact("drug_metabolized_by", "warfarin", "CYP2C9")
session.add_fact("inhibits", "fluconazole", "CYP2C9")

# Reason
session.add_rule("danger(P,D) :- patient_takes(P,D,_), drug_metabolized_by(D,E,_), inhibits(I,E,_)")
result = session.derive()
print(result)  # DeriveResult(count=1, cycles=82, time_us=0.82)

# Query
q = session.query("danger")
print(q)  # QueryResult(pred=danger, matches=1)

Compiler Pipeline

NXLang (.nx)
    |
    v
Lexer (40+ token types) -> Parser (recursive descent) -> Type Checker
    |
    v
NXIR (SSA-form intermediate representation with engine tags)
    |
    v
Optimizer (dead code elimination, parallel region detection)
    |
    +---> Simulation Backends (Brian2, Datalog, NumPyro)
    |
    +---> FPGA Backend (NEW)
              |
              +---> Symbol Table (names -> 8-bit pred IDs, 16-bit constants)
              +---> Variable Encoder (Datalog rules -> packed register format)
              +---> Hardware Encoder (register write sequences)
              |
              v
         NXB Binary / Tcl Script / JSON / C Header
              |
              v
         HAL (JTAG | PCIe | USB | Sim)
              |
              v
         NXPU Silicon (ZCU106 FPGA)

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Architecture

nxpu_axi_slave (42 registers, AXI4-Lite)
    |
    +-- CAM (256 entries, 56-bit, O(1) parallel search)
    |     +-- popcount + priority_enc
    |
    +-- rule_eval (12-state FSM, 4 body atoms, 8 variables)
    |     +-- unifier (combinational pattern match)
    |
    +-- nm_top (16 LIF spiking neurons)
    |     +-- synapse_xbar + neuron_array + stdp
    |
    +-- concept_formation (autonomous concept discovery)
    +-- feedback_bus (NM <-> SLU <-> CSE FIFO paths)
    +-- meta_rule (self-modifying rule engine)
    +-- pattern_comparator (cross-domain analogy)
    +-- semantic_tokenizer + triple_extractor + trace_to_text (NLU)
    +-- cycle_counter (hardware performance measurement)

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Use Cases

Market	Problem	NXPU Solution	Market Size
Cybersecurity	Real-time threat inference at network edge	CAM+rules in firewall silicon, line-rate reasoning	$22B
Healthcare	Drug interaction detection without hallucination	100% accurate, explainable, FDA-friendly	$14B
IAM/Zero Trust	Hardware-accelerated policy evaluation	10ns per policy check vs microseconds in software	$5B
DevSecOps	Transitive dependency vulnerability scanning	3-hop chain analysis in microseconds	$500M
Legal/Compliance	GDPR/HIPAA violation detection	Deterministic, auditable, real-time	$10B
Industrial Safety	Deterministic safety interlocks	Hardware-level correctness guarantee	$8B
Edge IoT	On-device reasoning at milliwatts	0.165 uJ per derivation (ASIC projection)	$50B+

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Why Not Just Use a GPU?

	GPU (H100)	NXPU
Core operation	Matrix multiplication	Pattern matching + logical inference
Power	700W	~1W (FPGA) / ~0.1W (ASIC)
Accuracy on reasoning	80-90% (hallucinates 10-20%)	100% (sound deduction)
Training	Weeks on 10K+ GPUs	None
Energy/inference	390,000 uJ/token	1.65 uJ/derivation
Explainability	Black box	Every step traceable
Edge-deployable	No (700W)	Yes (<1W)

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Project Structure

nxpu-ai/
  nxpu/
    nxlang/             NXLang compiler
      lexer.py            Tokenizer (40+ token types)
      parser.py           Recursive descent parser
      ast_nodes.py        AST node types
      type_checker.py     Validation
      nxir.py             SSA-form IR with engine tags
      optimizer.py        DCE + parallel region detection
      backends.py         Simulation backends (Brian2, Datalog, NumPyro)
      hw_backend.py       FPGA backend (Tcl, NXB, JSON, C)
      hw_encoder.py       Register write sequence generator
      var_encoder.py      Datalog rule -> hardware format encoder
      symbol_table.py     Name -> numeric ID mapping
    hal/                Hardware abstraction layer
      base.py             Abstract transport interface
      jtag_hal.py         SSH + Vivado JTAG transport
      sim_hal.py          Software simulation transport
    runtime.py          Python SDK (Session, DeriveResult, QueryResult)
    engines/            NM, SLU, CSE, Orchestrator implementations
    benchmarks/         15+ benchmark scripts
    examples/           NXLang example programs
      pharma_safety.nx    Drug interaction detection
      security_rules.nx   Network threat assessment
      reasoning_test.nx   4-domain novel reasoning
      stress_test_hard.nx 5 commercial-grade challenges
    nxhub/              Knowledge package registry
    nxsim/              Energy and latency models
  nxc.py              CLI (compile, hw-compile, deploy, repl, query, status)
  docs/               Documentation + whitepaper
  website/            Landing page

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Quick Start

# Install
git clone https://github.com/dyber-pqc/NXPU.git
cd NXPU
pip install -r requirements.txt

# Compile a program for FPGA
python nxc.py hw-compile nxpu/examples/pharma_safety.nx --format tcl

# Run in simulation (no hardware needed)
python nxc.py repl --transport sim

# Run all benchmarks
python -m nxpu.benchmarks.run_all

# Deploy to ZCU106 FPGA (requires hardware)
python nxc.py deploy nxpu/examples/pharma_safety.nx --transport jtag --host 192.168.0.142

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Case Studies

• Pharmacovigilance -- Detected warfarin-fluconazole interaction (a real clinical danger) through 4-body-atom reasoning in 164 cycles. 100% accuracy, 0 false positives.
• Math Reasoning -- 12/12 correct technique selections across arithmetic, algebra, geometry, calculus, differential equations, and statistics.
• Claims & Benchmarks -- Full analysis of provable claims backed by silicon data.

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Hardware

• FPGA Prototype: Xilinx ZCU106 (xczu7ev-ffvc1156-2-e)
• Clock: 100 MHz, WNS = +1.651 ns (timing met)
• Subsystems: 15+ Verilog modules, 42 AXI registers
• RTL: nxpu-rtl/ directory (CAM, rule_eval, unifier, nm_top, concept_formation, feedback_bus, meta_rule, pattern_comparator, NLU pipeline)

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Competitive Landscape

Nothing like NXPU exists as a product. The closest:

	GPU/TPU	Neuromorphic (Loihi/Akida)	TCAM chips	CoCoSys (DARPA)	NXPU
Logical inference	No	No	No	Research	Yes, silicon-proven
Variable binding	No	No	No	Unknown	Yes
Zero hallucination	No	No	N/A	No	Yes
Spiking neural net	No	Yes	No	Partial	Yes
Concept learning	No	No	No	Unknown	Yes
Cross-domain transfer	No	No	No	Unknown	Yes
Commercial product	Yes	Limited	Yes	No	In development

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Form Factor Roadmap

Phase	Form Factor	Timeline
Now	FPGA prototype (ZCU106)	Done
Next	IP license (Verilog RTL)	Ready
Then	M.2 AI accelerator module	2027
Future	ASIC (10nm/7nm)	2028

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Contact

Dyber, Inc. Zachary Kleckner, Founder/CTO Website | Whitepaper

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NXPU: Purpose-built silicon for deterministic AI reasoning. Zero training. Zero hallucination. 78x lower energy vs Intel Core Ultra 9.