This release has been yanked by its maintainers, and will be ignored by installers, except when explicitly specified.
Consider using release 1.2.48 instead.
Reason given by maintainers: generic bitcell array path broken on freepdk45/scn4m_subm, see issue #336
OpenRAM
An open-source static random access memory (SRAM) compiler.
What is OpenRAM?
OpenRAM is an award winning open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.
Documentation
Please see our documentation and let us know if anything needs updating.
Get Involved
- Port it to a new technology
- Report bugs by submitting Github issues
- Develop new features (see how to contribute)
- Submit code/fixes using a Github pull request
- Follow our project
- Read and cite our ICCAD paper
Further Help
License
OpenRAM is licensed under the BSD 3-Clause License.
Publications
- M. R. Guthaus, J. E. Stine, S. Ataei, B. Chen, B. Wu, M. Sarwar, "OpenRAM: An Open-Source Memory Compiler," Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 2016.
- S. Ataei, J. Stine, M. Guthaus, "A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS," International Conference on Computer Design (ICCD), 2016, pp. 499-506.
- E. Ebrahimi, M. Guthaus, J. Renau, "Timing Speculative SRAM," IEEE International Symposium on Circuits and Systems (ISCAS), 2017.
- B. Wu, J.E. Stine, M.R. Guthaus, "Fast and Area-Efficient Word-Line Optimization," IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
- B. Wu, M. Guthaus, "Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.
- H. Nichols, M. Grimes, J. Sowash, J. Cirimelli-Low, M. Guthaus "Automated Synthesis of Multi-Port Memories and Control," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.
- M. Guthaus, H. Nichols, J. Cirimelli-Low, J. Kunzler, B. Wu, "Enabling Design Technology Co-Optimization of SRAMs though Open-Source Software," IEEE International Electron Devices Meeting (IEDM), 2020.
- H. Nichols, "Statistical Modeling of SRAMs," M.S. Thesis, UCSC, 2022.
Contributors & Acknowledgment
- Matthew Guthaus from VLSIDA created the OpenRAM project and is the lead architect.
- James Stine from VLSIARCH co-founded the project.
- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera, Sage Walker
If I forgot to add you, please let me know!
1 maintainer
Metadata
1 maintainer
Release files for openram 1.2.50
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Source distribution (sdist)
| File | Size | Uploaded | Provenance | Actions |
|---|---|---|---|---|
| openram-1.2.50.tar.gz | 1.2 MB | Without provenance | Details for openram-1.2.50.tar.gz |
Built distribution (wheel)
| File | Interpreter | ABI | Platform | Actions Reset |
|---|---|---|---|---|
| openram-1.2.50-py3-none-any.whl | Python 3 | none | any | Details for openram-1.2.50-py3-none-any.whl |
Total release size: 3.1 MB
Release files / openram-1.2.50.tar.gz
| Download URL | openram-1.2.50.tar.gz |
|---|---|
| Size | 1.2 MB |
| Tags | Source |
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| Download URL | openram-1.2.50-py3-none-any.whl |
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| Size | 1.8 MB |
| Tags | Python 3 |
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