peakrdl-axil-master-vhdl 0.1.2

This repository implements a PeakRDL module that generates a VHDL AXI4Lite master from a SystemRDL file. The module generates an entity and a corresponding package which should be used together.

AXI4Lite Master Operation

The master takes a record with registers as an input called cfg_data_i and as soon as the valid flag cfg_valid_i is raised, the master starts to write registers to the correstonding memory locations which starts at the BASEADDR.

While in operation, the master raises the busy_o flag and deasserts the done_o flag. Once the master finishes writing registers, it raises the done_o flag and deasserts the busy_o flag.

The master checks for the response value and if the write is unsuccessful, the master repeats the write transaction for at most MAX_RETRY times. If it exceeds the number of repeating transactions, it raises the err_o flag for one clock cycle and returns to the initial state waiting for new input. If the AXI4Lite partner does not send a response for MAX_TIMEOUT clock cycles, the master raises the err_o flag for one clock cycle and returns to the initial state.

Local Installation

pip install .

Usage Example

peakrdl axil-master-vhdl <path/to/system.rdl> -o <output/path>