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A library for generating VHDL, designed for use in FPGAs

Project description

pywire is an easy-to-use Python library for generating VHDL, designed for use with FPGAs.

- Simple and complex functions
- Import components
- Generate timing files

Does not support:
- More than one clock

To install:
pip install pywire

from pywire import *

x = Signal(1, io=“out”, port=“P7”)
y = Signal(1, io=“in”, port=“P42”)

def inverter(x):
return 1-x, y)

The full documentation can be found at

Project details

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