routertl 3.9.0

FPGA build system with 2,000+ IP package manager. Cross-language dependency resolution, smart linting, multi-vendor synthesis — one pip install.

RouteRTL
The FPGA build system that reads your HDL and figures it out.

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pip install routertl

RouteRTL is a command-line FPGA SDK with a built-in IP package manager. Install a UART core, an AXI interconnect, or a full RISC-V SoC — dependencies are resolved automatically from the source code. No manual file lists. No compilation order. No "works on my machine."

Install an IP, See It Work

rr init --non-interactive --no-venv
rr pkg add open-logic/olo_intf_uart
rr lint olo_intf_uart

  + open-logic/olo_intf_uart ^4.4.1
  Resolving 1 package(s) from https://registry.routertl.dev
    open-logic/olo_intf_uart: ^4.4.1 -> 4.4.1
  Written ip.lock (1 packages)

  Lint passed  (ghdl)

RouteRTL cloned the package, resolved 8 transitive VHDL dependencies, compiled them in the correct library order, and linted — all from one command.

rr hierarchy --forest

  olo_intf_uart  (olo_intf_uart.vhd, 8 files)
  |-- olo_base_strobe_gen
  |   +-- [1 pkgs: olo_base_pkg_math]
  |-- olo_intf_sync
  |   +-- [1 pkgs: olo_base_pkg_attribute]
  +-- [3 pkgs: olo_base_pkg_logic, olo_base_pkg_math, olo_base_pkg_string]

2,000+ IP Blocks. Cross-Language Dependency Resolution.

rr pkg search ethernet                    # browse the catalog
rr pkg add alexforencich/eth_arb_mux      # Verilog — deps auto-expanded
rr pkg add grlib/greth                    # VHDL — library deps auto-resolved
rr pkg add openhwgroup/cva6              # SystemVerilog — full SoC

The registry knows what every package provides and what it needs — both VHDL libraries and Verilog modules. When you install a package, RouteRTL:

1. Queries the registry for dependency metadata
2. Resolves missing libraries and modules to their provider packages
3. Auto-installs transitive dependencies
4. Compiles everything in the correct order
5. Lints and reports results

Pre-packaged from open-logic, GRLIB (LEON/NOEL-V), alexforencich (verilog-ethernet, verilog-axi), OpenHW Group (CVA6/CORE-V), VUnit, Enclustra, and more. Pinned by commit SHA in a lock file.

What You Get

IP Package Manager	2,000+ blocks, cross-language dependency graphs, lock files, rr pkg search/add/update
Auto-Discovery	Point at a source tree — VHDL, Verilog, SystemVerilog hierarchy resolved automatically
Multi-Vendor Synthesis	Vivado, Quartus (Pro/Standard), Radiant, Libero — change one word in project.yml
Cocotb 2.0+ Simulation	rr sim, rr testgen, rr watch — NVC, GHDL, Verilator, Icarus, QuestaSim
Protocol Drivers	UART, SPI, I2C, QSPI, AXI4-Lite, AXI4, Avalon-MM — included, zero extra deps
Smart Linting	Hierarchy-aware, incremental, multi-pass — rr lint just works
Code Generation	Bus bridges (AXI/Avalon/Native), register banks (VHDL + C headers + HTML docs)
Pre-Commit Gates	Lint + simulate + YAML check on every commit
Docker EDA Provisioning	rr docker install vivado — headless vendor tool setup, same environment everywhere

Battle-Tested

Validated against real-world codebases with zero configuration beyond rr init:

• open-logic — 77 entities, 4 IP areas, flat multi-root library. 77/77 files resolved, 0 violations.
• NEORV32 — 56 entities, deep monolithic SoC, complex generics. 0 violations.

The CLI

rr init                       # scaffold a project
rr hierarchy --forest         # design hierarchy
rr lint                       # smart lint (GHDL + Verilator)
rr sim test_my_module         # simulate (cocotb 2.0+)
rr testgen edge_counter       # generate test boilerplate
rr watch                      # re-run on save
rr synth run my_top           # synthesize
rr implementation             # place & route
rr bitstream                  # generate bitstream
rr report                     # utilization & timing
rr deps graph                 # dependency visualization
rr pkg search / add / update  # IP package manager
rr migrate                    # import existing Vivado/Quartus projects
rr docker install vivado      # headless EDA provisioning
rr doctor                     # toolchain health check

Both routertl and rr work as entry points.

Quick Start

1. Install

pip install routertl

For platform-specific instructions (Linux, WSL2, macOS), see the Installation Guide.

2. Initialize

rr init --name my_project --vendor xilinx --part xc7z020clg400-1

Creates project.yml, directory structure, virtual environment, and pre-commit hooks.

Existing project? rr migrate imports Vivado and Quartus projects. Or run rr init inside an existing repo and adjust the paths: block.

3. Add IP and Build

rr pkg add open-logic/olo_base_fifo_sync  # install with deps
rr lint                                    # verify everything compiles
rr sim test_my_module                      # run simulation
rr synth run my_top                        # synthesize

Simulation API

from routertl.sim import Tb, run_simulation, UartSource, SignalCollector

@cocotb.test()
async def test_my_module(dut):
    tb = Tb(dut)
    await tb.start_clock()
    await tb.reset()
    # Your test logic here

Native protocol drivers included: AXI4-Lite, AXI4, Avalon-MM, Native Memory, UART, SPI, I2C — with passive monitors and bridge scoreboards.

Who Is This For?

• FPGA engineers who want reproducible, scriptable builds instead of vendor GUI projects
• Teams integrating FPGA into CI/CD pipelines
• Multi-vendor shops targeting Xilinx, Intel/Altera, Lattice, and Microchip from one project.yml

Documentation

I want to...

Goal	Link
Create my first project	First Steps Tutorial
Write a simulation	Cocotb Quickstart
Use a protocol driver	Driver Cookbook
Understand project.yml	project.yml Reference
Migrate an existing project	Existing Project Migration
Fix an error	Troubleshooting
Browse all docs	Documentation Index

Prerequisites

Tool	Required	Notes
Python 3.10+	Yes	CLI and simulation framework
Git	Yes	Version control and dependency tracking
NVC	Recommended	VHDL simulator for Cocotb 2.0+ (.deb)
GHDL	Recommended	VHDL analyzer (fast linting)
Vendor tools	Optional	Vivado / Quartus / Radiant / Libero — or rr docker install

Acknowledgments

RouteRTL builds on the work of several outstanding open-source projects. We gratefully acknowledge:

Project	Role in RouteRTL
NVC	Primary VHDL simulator for Cocotb 2.0+ simulation
GHDL	VHDL analysis, linting, and secondary simulation backend
Cocotb	Python-based verification framework powering rr sim
Verilator	Verilog/SystemVerilog simulation and linting backend
Icarus Verilog	Lightweight Verilog simulation backend
xpm_vhdl	Open-source VHDL implementation of Xilinx XPM macros
Rich	Terminal formatting for CLI output
Jinja2	Template engine for code generation

RouteRTL would not be possible without these projects and their maintainers.

Contributing

The best way to contribute is to use RouteRTL and tell us what breaks. To report a bug, suggest a feature, or share how you're using it, email [e-mail]. Include the output of rr doctor when reporting issues.

See CONTRIBUTING.md for details.

Contact

Built and maintained by Daniel J. Mazure — routertl.dev · [e-mail]

Licensing

RouteRTL uses a dual-license model:

Component	License	You can...
CLI, build system, cocotb drivers, hooks, docs	MIT	Use, modify, redistribute — no restrictions
Compiled core (routertl_core/*.so)	PolyForm Shield 1.0.0	Use for any purpose except building a competing product

Licensing FAQ

Question	Answer
Can I use RouteRTL commercially?	Yes — use it to build, simulate, and ship your FPGA products without restriction.
Can I modify the CLI or build system?	Yes — they're MIT-licensed. Fork, extend, contribute PRs — all welcome.
Can I decompile the .so modules?	No — that violates the PolyForm Shield license.
Can I redistribute the PyPI wheel?	Yes — as-is, per standard PyPI terms.
What counts as "competing"?	Building and distributing an FPGA SDK that substitutes for RouteRTL. Using RouteRTL to build your own product is not competing.

Copyright 2026 Daniel J. Mazure