silica-eda 0.4.0

AI-native EDA environment · MCP server for hardware design and verification

What it does

Silica is an MCP server that gives coding agents structured access to an EDA toolchain. The agent lints, simulates, proves, synthesizes, places and routes, programs a board and reads its UART through MCP tools, and gets parsed results back (errors with file and line, timing per clock, utilization, inferred memories, counterexample traces) instead of raw logs.

That closes the loop without copy-paste: run the simulation, read the failure, fix the RTL, re-run. The server also tells the agent the order to work in and the pitfalls to avoid, and a doctor tool reports which EDA tools are installed and how to install the rest.

Silica drives tools you install yourself: open-source tools (mostly from OSS CAD Suite), and commercial ones (VCS, Questa, Xcelium, Vivado, …) when they're on PATH. How well each is tested is listed under Supported tools.

What works today

The full flow has been run end to end on a Digilent Arty A7-100T (Xilinx Artix-7) with a PicoRV32 RISC-V SoC whose firmware prints a banner, echoes UART input and drives LEDs from a timer:

1. RTL and lint: Verilator, Verible and svlint, with Verilator elaborating the whole multi-file design.
2. Simulation: Icarus and Verilator running the real firmware from $readmemh, with waveform (read_waveform) and line coverage (read_coverage).
3. Formal: SymbiYosys prove, cover and bounded checks on the UART and FIFO, a deliberately false assertion reported as FAIL with its counterexample, and eqy equivalence.
4. Synthesis: Yosys synth_xilinx, with utilization and the firmware ROM reported as block RAM with init data.
5. Place and route: openXC7's nextpnr-xilinx (100 MHz target, routed at 153 MHz), and the .bit assembled with fpga-as.
6. Programming: program_device (openFPGALoader) into SRAM, with the FPGA's DONE status checked.
7. Serial check: capture_serial confirming the banner and the echo over the board's UART.

These runs were manual, on one machine (OSS CAD Suite 2026-10-14, openXC7 toolchain-nix 1.0.0, Verible v0.0-4296, svlint 0.9.5). CI covers the open-source tools in a weekly integration job; see Supported tools.

Known limitations

• Vivado is synthesis only: there's no implementation or bitstream step.
• VCS, Questa and Xcelium adapters are tested only with mocked tool calls, never against a real install; the same goes for Quartus, DC Shell, JasperGold, VC Formal, SpyGlass and Verdi. If one misbehaves, please open an issue with the tool version and output.
• iCE40 and ECP5 place and route returns nextpnr's .asc/.textcfg; silica doesn't run icepack/ecppack, so those can't be loaded with program_device directly. get_project_structure doesn't list iCE40 .pcf files.
• cocotb needs a Python whose glibc is compatible with the simulator it loads into. With OSS CAD Suite's simulators and a newer system Python (glibc newer than the suite's), run_cocotb fails at import.
• Formal: an UNKNOWN prove with induction_failures is inconclusive (k-induction didn't close), not a bug. Deep bounded checks can be slow; 120 steps on the example UART took 16 minutes.
• Serial: capture_serial needs the port named explicitly and read/write access to it. A boot banner is usually missed by a capture started after programming.
• Windows: the serial existence and permission pre-checks are POSIX-only, and the pty-based serial tests skip there.

Quick start

1. Add silica to your agent. Follow Install in your agent: each client launches uvx silica-eda@latest. (With pip instead: pip install silica-eda, then silica setup writes the config for Claude Desktop, Claude Code, Cursor, Zed, Windsurf, OpenCode or Gemini CLI.)

2. Install the EDA tools you need: OSS CAD Suite for most open-source tools, Verible and svlint for linting, openXC7 for Xilinx place and route. Then ask the agent to run doctor.

3. Try the UART example in examples/uart/:

   Run the UART TX simulation in examples/uart/ and tell me if it passes.

   Then break it and let the agent find the bug:

   In examples/uart/uart_tx.sv, change the DATA state's shift to shift_reg <= {shift_reg[6:0], 1'b0};. Run the simulation, find the bug and fix it.

   The testbench then prints [FAIL] lines such as bit[2] is 0, expected 1, and the agent should trace them to the shift direction.

Install in your agent

Every client below starts the server with uvx silica-eda@latest: uv downloads silica into a cached environment on first use and picks up new releases when the client next starts the server. Install uv first. uvx silica-eda needs a silica-eda release newer than 0.3.1; on 0.3.1 use uvx --from silica-eda@latest silica instead.

silica drives EDA tools you install separately (Verilator, Yosys, SymbiYosys, nextpnr, …); see Installing the EDA tools. Once connected, ask the agent to run the doctor tool: it lists what's installed and how to install what's missing.

/plugin marketplace add simaanc/silica-eda
/plugin install silica-eda@silica-eda

claude mcp add --transport stdio --scope user silica -- uvx silica-eda@latest

{
  "mcpServers": {
    "silica": {
      "command": "uvx",
      "args": ["silica-eda@latest"]
    }
  }
}

codex mcp add silica -- uvx silica-eda@latest

[mcp_servers.silica]
command = "uvx"
args = ["silica-eda@latest"]
# The first launch downloads silica; Codex's default start timeout is 10 s.
startup_timeout_sec = 60

{
  "mcpServers": {
    "silica": {
      "type": "stdio",
      "command": "uvx",
      "args": ["silica-eda@latest"]
    }
  }
}

cursor://anysphere.cursor-deeplink/mcp/install?name=silica&config=eyJjb21tYW5kIjoidXZ4IiwiYXJncyI6WyJzaWxpY2EtZWRhQGxhdGVzdCJdfQ==

code --add-mcp '{"name":"silica","type":"stdio","command":"uvx","args":["silica-eda@latest"]}'

{
  "servers": {
    "silica": {
      "type": "stdio",
      "command": "uvx",
      "args": ["silica-eda@latest"]
    }
  }
}

gemini mcp add -s user silica uvx silica-eda@latest

{
  "mcpServers": {
    "silica": {
      "command": "uvx",
      "args": ["silica-eda@latest"]
    }
  }
}

Optional extras. capture_serial needs pyserial and run_cocotb needs cocotb. With uvx, add them to the arguments: "args": ["--with", "pyserial", "silica-eda@latest"] (or --with cocotb). With pip, install silica-eda[serial] or silica-eda[cocotb].

Pin a version or roll back. Replace silica-eda@latest with an exact version, silica-eda@<version> (for example uvx silica-eda@0.4.0 once that release exists), and the client keeps running that release until you change it. To roll back after a bad release, pin the previous version the same way. The Claude Code plugin always runs @latest; to pin there, add the server with claude mcp add and a pinned version instead of installing the plugin. Releases are listed on PyPI and in the changelog.

MCP tools

Prompts with step-by-step triage scripts: debug_simulation_failure, debug_formal_failure, write_testbench, generate_assertions, close_timing, cdc_review.

Supported tools

"Real tool in CI" means the weekly integration workflow runs it from OSS CAD Suite. "Tested on hardware" means the manual Arty A7-100T run described under What works today. "Mocked only" means unit tests with captured or representative output, never a real install.

Checking a design on hardware

program_device and capture_serial close the loop on a real board: program it, then read what the design prints. capture_serial needs pyserial, from the serial extra:

pip install "silica-eda[serial]"

A typical check after run_place_route has produced a bitstream, here checking that the firmware on an Arty A7-100T echoes what it receives:

program_device(bitstream="build/soc.bit", board="arty_a7_100t")
  -> {"success": true, ...}

capture_serial(port="/dev/serial/by-id/usb-Digilent_Digilent_USB_Device_<serial>-if01-port0",
               baud=115200, duration=6, send="hello silica\r", send_delay=0.5,
               expect="hello silica")
  -> {"matched": true, "match": "hello silica", "elapsed_s": 0.53,
      "lines": [{"t": 0.526, "text": "hello silica"}], ...}

Name the port explicitly; silica never scans for serial devices. On boards with an FTDI JTAG+UART bridge (Digilent Arty, Basys, Nexys) the UART is the second interface, if01. The design starts running as soon as programming finishes, so a banner printed at boot is usually gone before a capture opened afterwards: send something the firmware answers (as above), or press the board's reset button during the capture. If the port is missing or your user can't open it, the result carries an error and a fix such as:

sudo setfacl -m u:you:rw /dev/ttyUSB1   (temporary: lasts until the device is unplugged);
permanent: sudo usermod -aG uucp you, then log out and back in

Xilinx 7-series flow

With openXC7 set up, an Artix-7 design goes from RTL to a programmed board in three calls:

synthesize(top_module="soc_top", files=["rtl/soc_top.sv", ...], target="xilinx", tool="yosys")
  -> {"netlist": "/tmp/silica_synth_.../netlist.json", "memories": [...], ...}

run_place_route(netlist="<netlist>", arch="xilinx", device="xc7a100tcsg324-1",
                constraint="arty.xdc", freq=100, output="build/soc.bit")
  -> {"output": "build/soc.bit", "timing_summary": {"clocks": [{"max_freq_mhz": 153.4, "pass": true}]}, ...}

program_device(bitstream="build/soc.bit", board="arty_a7_100t")
  -> {"success": true, ...}

device is the full part with speed grade. For the Arty A7-100T the openFPGALoader board is arty_a7_100t (arty is the 35T).

Configuration

Controlling tool selection

By default every detected tool is available and auto picks the best one (open-source first). To control this per category, edit ~/.silica/config.toml:

[tools.simulation]
priority = ["verilator", "iverilog"]   # ordering for auto-selection
enabled  = ["verilator", "iverilog"]   # allowlist — everything else is blocked

priority reorders what auto tries. enabled is an enforced allowlist: tools not on it can't be used even when the model asks for one explicitly — the request is rejected with an error naming the tool and what's enabled, so the model can retry with an allowed one. Useful when a machine has commercial tools installed that shouldn't be run (license pools, air-gapped flows). Leave enabled empty or unset for no restriction.

Categories: simulation, synthesis, place_route, formal, lint, format, waveform, program.

Guardrails

Built for pointing an autonomous agent at a real repo:

• File access is confined to the project directory — read_rtl, write_rtl, format_rtl, get_constraints, search_rtl and get_project_structure reject absolute or .. paths that escape the project root (SILICA_PROJECT_ROOT, the project.root config key, or the directory the server was started in). Relative paths are resolved against that root.
• Writes are diff-first — write_rtl defaults to a dry run that returns a unified diff; nothing touches disk until explicitly confirmed.
• A hung tool never kills the server — every tool call has a timeout and returns a structured error instead of crashing the session.

CLI

Versioning and compatibility

silica follows Semantic Versioning, applied to what MCP clients and agents depend on: tool names, their parameters, and the fields in their results. The same rules hold for 0.x releases.

• Within a major version no tool is renamed or removed, no parameter is removed or made required, and no result field is removed or renamed. Minor releases may add tools, optional parameters and result fields.
• Deprecations are announced in CHANGELOG.md and in the affected tool's description at least one minor release before the change ships in the next major version.
• Every user-visible change is listed in the changelog when it merges, under "Unreleased", and moves under the version heading at release.

Development

git clone https://github.com/simaanc/silica-eda
cd silica-eda
uv sync                                       # editable install + dev deps
uv run ruff check silica/ tests/ scripts/
uv run pytest tests/ -q                       # integration tests skip tools that aren't installed
uv run silica serve                           # run the server from the checkout

See CONTRIBUTING.md for conventions, docs/architecture.md for the code layout, and RELEASING.md for releases.

License

silica is licensed under the GNU Affero General Public License v3.0 (AGPL-3.0-only). You can use, modify and redistribute it, including commercially. If you distribute a modified version, or run one as a service that others interact with over a network, you must make your changes' source available under the same license.