tapa 0.0.20220505.1

Extending High-Level Synthesis for Task-Parallel Programs

TAPA

TAPA is a high-performance fast-compiling HLS framework that is fully compatible with the Xilinx Vitis/Vivado workflow.

• TAPA takes in a task-parallel dataflow program in C++ written in Vitis HLS syntax and additional TAPA APIs.
  • Compared to Vitis HLS, TAPA supports more flexible memory access patterns and runtime burst detection.
• TAPA extracts parallel components of the program and invokes Vitis HLS to compile each component simultaneously.
  • TAPA compiles 7× faster than Vitis HLS. In some cases, TAPA reduces a 10-hour Vitis compilation to 10 minutes.
• TAPA invokes the AutoBridge floorplanner to floorplan the dataflow program and pipeline the global data links accordingly.
  • With AutoBridge, TAPA achieves 2× higher the frequency on average compared to Vivado.
• TAPA supports a customized fast C-RTL simulation plug-in.
  • 10× faster than Vitis to setup the simulation.
• TAPA generates an xo object that is fully compatible as the input to the Vitis v++ compiler for bitstream generation.
  • [in-progress] TAPA is integrating the parallel physical implementation tool RapidStream.

Successful Cases

• Serpens, to appear in DAC'22, achieves 270 MHz on the Xilinx Alveo U280 HBM board when using 24 HBM channels. The Vivado baseline failed in routing.
• Sextans, FPGA'22, achieves 260 MHz on the Xilinx Alveo U250 board when using 4 DDR channels. The Vivado baseline achieves only 189 MHz.
• SPLAG, FPGA'22, achieves up to a 4.9× speedup over state-of-the-art FPGA accelerators, up to a 2.6× speedup over 32-thread CPU running at 4.4 GHz, and up to a 0.9× speedup over an A100 GPU (that has 4.1× power budget and 3.4× HBM bandwidth).
• AutoSA Systolic-Array Compiler, FPGA'21:
• KNN, FPT'20, achieves 252 MHz on the Xilinx Alveo U280 board. The Vivado baseline achieves only 165 MHz.

Getting Started

• Installation
• Tutorial
• API Reference

Related Publications

• Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong. Extending High-Level Synthesis for Task-Parallel Programs. In FCCM, 2021. [PDF] [Code] [Slides] [Video]
• Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong. AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. In FPGA, 2021. (Best Paper Award) [PDF] [Code] [Slides] [Video]