Picker

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Picker exports Verilog/SystemVerilog designs as Python, C++, Java, Scala, Go, or Lua modules, so you can write hardware tests in a familiar language. Tests can read and write signals, advance clocks, check results, and save waveforms. Picker also generates transaction bridges between Python and UVM.

The Python distribution is uc-picker; the command remains picker. It depends on uc-xcomm and SWIG.

Get started

Install Picker, then follow the adder tutorial to run your first test. From the repository root, export a Python module:

picker export example/Adder/Adder.v --sname Adder --lang python \
    --sim verilator --tdir build/docs-adder/Adder --autobuild false
make -C build/docs-adder/Adder -j4

Create a test in the generated package's parent directory to assign inputs by port name and check outputs. The tutorial includes a complete script and expected results.

Documentation

English documentation · 完整中文文档

• Use Picker: export RTL, clocks and waveforms, internal signals, languages, UVM.
• Look up an interface: CLI, DUT API, troubleshooting.
• Develop Picker: how it works, contributing and tests, documentation and Wiki.

Community

Report issues and suggestions through GitHub Issues. The community QQ group is 600480230. More verification resources are available in the MLVP documentation.

Code of conduct · Security reports · License