Verilog parser for Python
Lark based parser for Verilog netlists (structural Verilog without behavioral statements). This is meant to be used to read netlists as generated by HDL logic synthesizers such as Yosys.
Example
from verilog_parser.parser import parse_verilog
ast = parse_verilog(open(verilog_file_path).read())
Install
From PyPI:
pip install verilog-parser
From git:
pip install git+https://codeberg.org/tok/py-verilog-parser
From git for development:
git clone https://codeberg.org/tok/py-verilog-parser
cd py-verilog-parser
pip install --editable .
1 maintainer
Metadata
1 maintainer
Release files for verilog-parser 0.0.7
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Source distribution (sdist)
| File | Size | Uploaded | |
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| verilog_parser-0.0.7.tar.gz | 7.2 kB | Details |
Release files / verilog_parser-0.0.7.tar.gz
| Download URL | verilog_parser-0.0.7.tar.gz |
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| Size | 7.2 kB |
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