Parser for structural verilog.
Project description
Verilog parser for Python
Lark based parser for Verilog netlists (structural Verilog without behavioral statements). This is meant to be used to read netlists as generated by HDL logic synthesizers such as Yosys.
Example
from verilog_parser.parser import parse_verilog
ast = parse_verilog(open(verilog_file_path).read())
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