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Easy-To-Use SystemVerilog Parser

Features

  • Extract Port Lists
  • Extract Parameters
  • Extract Submodule Instances and their connections
  • ifdef support
  • Standards: IEEE 1800-2009 SystemVerilog

Limitations

  • No Syntax Checks - Source Code files must be syntactically correct
  • No Full Parser - This parser intends to be simple and just extract some information from the source code. Fast and Simple.

Installation

Installing it is pretty easy:

pip install hdl-parser

Authors

Usage

See Usage Documentation

Metadata

Release files for hdl-parser 1.1.0

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Source distribution (sdist)

Source distribution for hdl-parser 1.1.0
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hdl_parser-1.1.0.tar.gz 30.1 kB Details

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Table of built distributions (wheels) for hdl-parser 1.1.0
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hdl_parser-1.1.0-py3-none-any.whl Python 3 none any Details

Total release size: 63.5 kB

Release files / hdl_parser-1.1.0.tar.gz

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1.1.0 This release

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0.6.1

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