Parser for KiCad schematic netlists.
Module and utilities for manipulating part fields in KiCad files.
A Python package for textually describing electronic circuit schematics.
Build cost spreadsheet for a KiCad project.
Peek at signals in a MyHDL digital system simulation.
Part creator for KiCad.
MyHDL hardware design language encased in the tasty PygMyHDL wrapper.
Generate pin assignment constraints for a given combination of XESS peripheral + motherboard + daughterboard.
A set of tools to manage all the crap for the CAT Board.
Tools and classes for interfacing with XESS FPGA boards via USB.