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Check VHDL code for common codestyle problems.

Rules include:

  • Signals, variables, ports, types, subtypes, etc. must be lowercase.

  • Constants and generics must be uppercase.

  • Entities, architectures and packages must be “mixedcase” (may be 100% uppercase, but not 100% lowercase).

  • Ports must be suffixed using _i, _o or _io denoting its kind.

  • Labels must be placed in a separated line. Exception: component instantiation.

  • End statements must be documented indicating what are finishing.

  • Buffer ports are forbidden.

  • VHDL constructions of the “entity xxxx is” and similars must be in one line. You can’t put “entity xxxxx” in one line and “is” in another.

  • No more than one VHDL construction is allowed in one line of code.

See <http://fpgalibre.sourceforge.net/ingles.html#tp46> for more information.

Metadata

Release files for VHDLLintBear 0.8.0.1470652900

For a detailed explanation of source distributions (sdists) and built distributions (wheels), please see the package formats documentation.

Source distribution (sdist)

Source distribution for VHDLLintBear 0.8.0.1470652900
File Size Uploaded
VHDLLintBear-0.8.0.1470652900.tar.gz 2.4 kB Details

Built distribution (wheel)

Table of built distributions (wheels) for VHDLLintBear 0.8.0.1470652900
File Interpreter ABI Platform
VHDLLintBear-0.8.0.1470652900-py3-none-any.whl Python 3 none any Details

Total release size: 7.2 kB

Release files / VHDLLintBear-0.8.0.1470652900.tar.gz

Download URL VHDLLintBear-0.8.0.1470652900.tar.gz
Size 2.4 kB
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Release files / VHDLLintBear-0.8.0.1470652900-py3-none-any.whl

Download URL VHDLLintBear-0.8.0.1470652900-py3-none-any.whl
Size 4.8 kB
Tags Python 3
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7b5ffeb2e5ad0038bee291824f2ddf121673185d8cd5c639bfbc90af6c5c88a9
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