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Project Description

Verilog is a Hardware Description Language (HDL) used to model digital logic. While simulating logic circuits, the values of signals can be written out to a Value Change Dump (VCD) file. This module can be used to parse a VCD file so that further analysis can be performed on the simulation data. The entire VCD file can be stored in a Python data structure and manipulated using standard hash and array operations.

More details in the module file : Verilog_VCD.py .

Originally written in Perl by Gene Sullivan (gsullivan@cpan.org) . Translated into Python by Sameer Gauria (sgauria+python@gmail.com) . Patches submitted by Scott Chin, Sylvain Guilley, Bogdan Tabacaru, Andrew Becker, and a substantial performance improvement by Matthew Clapp.

Release History

Release History

1.11

This version

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1.10

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1.09

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1.08

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1.07

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1.06

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1.05

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1.04

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1.03

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1.02

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1.01

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1.0

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Download Files

Download Files

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File Name & Checksum SHA256 Checksum Help Version File Type Upload Date
Verilog_VCD-1.11.tar.gz (6.1 kB) Copy SHA256 Checksum SHA256 Source Oct 31, 2016

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