Skip to main content

Module to Parse VCD (Value-Change-Dump) files

Project description

Verilog is a Hardware Description Language (HDL) used to model digital logic. While simulating logic circuits, the values of signals can be written out to a Value Change Dump (VCD) file. This module can be used to parse a VCD file so that further analysis can be performed on the simulation data. The entire VCD file can be stored in a Python data structure and manipulated using standard hash and array operations.

More details in the module file : Verilog_VCD.py .

Originally written in Perl by Gene Sullivan (gsullivan@cpan.org) . Translated into Python by Sameer Gauria (sgauria+python@gmail.com) . Patches submitted by Scott Chin, Sylvain Guilley, Bogdan Tabacaru, Andrew Becker, and a substantial performance improvement by Matthew Clapp.

Project details


Download files

Download the file for your platform. If you're not sure which to choose, learn more about installing packages.

Filename, size & hash SHA256 hash help File type Python version Upload date
Verilog_VCD-1.11.tar.gz (6.1 kB) Copy SHA256 hash SHA256 Source None Oct 31, 2016

Supported by

Elastic Elastic Search Pingdom Pingdom Monitoring Google Google BigQuery Sentry Sentry Error logging AWS AWS Cloud computing DataDog DataDog Monitoring Fastly Fastly CDN DigiCert DigiCert EV certificate StatusPage StatusPage Status page