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cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.

Project description

cocotb is a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python.

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The current stable version of cocotb requires:

After installing these dependencies, the latest stable version of cocotb can be installed with pip.

pip install cocotb

For more details on installation, including prerequisites, see the documentation.

For details on how to install the development version of cocotb, see the preliminary documentation of the future release.

!!! Bus and Testbenching Components !!! The reusable bus interfaces and testbenching components have recently been moved to the cocotb-bus package. You can easily install these at the same time as cocotb by adding the bus extra install: pip install cocotb[bus].


As a first trivial introduction to cocotb, the following example "tests" a flip-flop.

First, we need a hardware design which we can test. For this example, create a file with SystemVerilog code for a simple D flip-flop. You could also use any other language a cocotb-supported simulator understands, e.g. VHDL.


`timescale 1us/1ns

module dff (
    output logic q,
    input logic clk, d

always @(posedge clk) begin
    q <= d;


An example of a simple randomized cocotb testbench:


import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge

async def test_dff_simple(dut):
    """ Test that d propagates to q """

    clock = Clock(dut.clk, 10, units="us")  # Create a 10us period clock on port clk
    cocotb.fork(clock.start())  # Start the clock

    for i in range(10):
        val = random.randint(0, 1)
        dut.d <= val  # Assign the random value val to the input port d
        await FallingEdge(dut.clk)
        assert dut.q.value == val, "output q was incorrect on the {}th cycle".format(i)

A simple Makefile:

# Makefile

VERILOG_SOURCES = $(shell pwd)/
MODULE = test_dff

include $(shell cocotb-config --makefiles)/Makefile.sim

In order to run the test with Icarus Verilog, execute:

make SIM=icarus


For more information please see the cocotb documentation and our wiki.

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