Control and Status Register map generator for FPGA/ASIC projects
Project description
Corsair
Corsair is a tool that makes it easy to organize and support control and status register (CSR) map for any FPGA/ASIC project. You just need to create and fill single CSR map description file once and then generate HDL code, headers, documentation and etc.
It is as easy as:
- Create CSR map description file or generate a template with Corsair:
corsair -t ip_csr.json
- Make changes to
ip_csr.json - Generate output artifacts:
corsair -i ip_csr.json -o ip_regmap.v ip_regmap.md
Supported input formats:
- JSON
- YAML
Supported output formats:
- JSON
- YAML
- (SOON) Verilog
- (SOON) Markdown
For more details about ways the tool can be used and how it works please refer the documentation at Read the docs.
Installation
You can install the latest stable version from pypi:
python3 -m pip install -U corsair
Development
Corsair is still under development. Please follow the Developers Guide.
License
Corsair is licensed under MIT License.
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