corsair 0.3.0

Control and Status Register map generator for FPGA/ASIC projects

Corsair

Corsair is a tool that makes it easy to organize and support control and status register (CSR) map for any FPGA/ASIC project. You just need to create and fill single CSR map description file once and then generate HDL code, headers, documentation and etc.

It is as easy as:

• Create CSR map description file or generate a template with Corsair:

corsair --template-regmap regs.json

• Make changes to regs.json
• Generate output artifacts:

corsair -r regs.json --hdl --lb-bridge --docs

• You will get:
  • Register map HDL code
  • Bridge to some standart interface (e.g. AXI-Lite, depends on configuration)
  • Document, describing the map

For more details about ways the tool can be used and how it works please refer the documentation at Read the docs.

Installation

Depending on your system, Python executable might be python or python3. If there any permissions issues, add --user key to the installation scripts.

You can install the latest stable release:

python3 -m pip install -U corsair

To install development verision satisfy dependencies first:

python3 -m pip install gitpython

Then you can use pip:

python3 -m pip install -U git+https://github.com/esynr3z/corsair.git

Or alternatively:

git clone https://github.com/esynr3z/corsair.git
cd corsair
python3 setup.py install

Development

Corsair is still under development. Please follow the Developers Guide.

License

Corsair is licensed under MIT License.