evas-sim 0.1.2

Event-driven Verilog-A Simulator — pure-Python behavioral simulation

EVAS — Event-driven Verilog-A Simulator

A lightweight, pure-Python behavioral simulator for digital/mixed-signal Verilog-A models. Event-driven. No C compiler, no ngspice, no KCL/KVL solver.

📖 Docs: evas.tokenzhang.com  |  中文

---

If you're a human — install with pip and jump to Quickstart.

If you're an AI agent — copy skills/evas-sim/ into your .claude/skills/ (Claude Code) or equivalent skills directory for your agent framework. The skill file gives you built-in knowledge of EVAS commands, supported Verilog-A features, and common failure modes so you can simulate and debug without guessing.

---

Installation

pip install evas-sim

Verify:

evas list        # prints all bundled examples

If evas is not on PATH, use python -m evas.

Quickstart

# Run a bundled example
evas run clk_div

# Run with a specific testbench (for multi-TB examples)
evas run digital_basics --tb tb_not_gate.scs

# Simulate your own netlist
evas simulate path/to/tb.scs -o output/mydesign

Output lands in ./output/<name>/ (bundled) or the -o directory (custom). Each run produces tran.csv (waveforms), one or more .png plots, and strobe.txt (log messages).

Bundled Examples

Name	Description
clk_div	Clock divider
clk_burst_gen	Clock burst generator
lfsr	Linear feedback shift register
noise_gen	Noise signal generator
ramp_gen	Ramp signal generator
edge_interval_timer	Edge-interval timer
d2b_4b	4-bit thermometer-to-binary decoder
dac_binary_clk_4b	4-bit binary DAC (clocked)
dac_therm_16b	16-bit thermometer DAC
adc_dac_ideal_4b	4-bit ideal ADC + DAC with sample-hold
comparator	StrongARM comparator + offset search algorithm
dwa_ptr_gen	DWA pointer generator
sar_adc_dac_weighted_8b	8-bit weighted SAR ADC + DAC
digital_basics	AND / OR / NOT gates, D flip-flop, inverter chain

Supported Verilog-A

Feature	Status
V(node) <+, V(a,b) differential	✅
@(cross(...)), @(above(...)), @(initial_step)	✅
transition() with delay / rise / fall	✅
for, if/else, begin/end, arrays, parameters	✅
`include, `define, `default_transition	✅
SI suffixes, math functions, string parameters	✅
I() <+, ddt(), idt(), q() <+	❌
AC/DC analysis, subcircuit hierarchy, transistors	❌

CSV Output Format

The save statement accepts optional per-signal format hints:

save vin:10e vout:6e clk:2e dout_code:d

Suffix	Format
:6e (default)	4.500000e-01
:Nf	fixed-point, N decimal places
:d	integer

Development

git clone https://github.com/Arcadia-1/EVAS.git
cd EVAS
pip install -e ".[dev]"
pytest tests/ -v

License

MIT — see LICENSE.