flote 0.1.0

Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.

Flote

🛸 Introduction

Flote is a hardware description language and Python framework for hardware simulation. It is designed to be friendly, simple, light and productive. More easy to use and learn than Verilog and VHDL. Using Flote, you can create integrated circuits component by using it's HDL and/or Python framework that work by the HLS (High Level Synthesis) concept.

Here is an example of a half adder in Flote:

comp halfAdder {
  in bit a;
  in bit b;

  out bit sum = a xor b;
  out bit carry = a and b;

}

⚙️ How it works

Flote's Evaluator uses a structure of a compiler's front-end to elaborate the component. It has a scanner, parser and a builder. This last one is responsible for build the component, an object that can be manipulated in Python and simulates the behavior of the integrated circuit. The model object it's a set of signals buses and uses event driven algorithm and dynamic programming to simulate the behavior of the circuit.

Using the HLS side, you can create the component "by hand". Also with the use of the Python package you can manipulate the signals and sava then in a waveform file.

🚀 Release

Flote is in beta development. You can see the latest releases in the GitHub repository.

📝 To Do List

• Make the simulator class
• Make EBNF for the language
• Make Scanner
• Make Parser
• Make Builder
• Make accept expressions
• Improve the algorithm of simulation
• Improve structure
• Improve declaration and assignment
• Improve Semantic Analysis
• Create waveform class
• Add line number in semantic errors
• Improve testbench methods
• Add multi-bit signals support
• Add multi-bit signals addressing support
• Add sub-components support
• Add Python calls support
• Improve HLS support
• Add manual time control
• Add others file types support for waveforms