flote 0.4.0

Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.

Flote

🛸 Introduction

Flote is a hardware description language and Python framework for hardware simulation. It is designed to be friendly, simple, light and productive. More easy to use and learn than Verilog and VHDL. Using Flote, you can create integrated circuits component by using it's HDL and/or Python framework that work by the HLS (High Level Synthesis) concept.

Here is an example of a half adder in Flote:

comp halfAdder {
  in bit a;
  in bit b;

  out bit sum = a xor b;
  out bit carry = a and b;

}

⚙️ How it works

Flote's Evaluator uses a structure of a compiler's front-end to elaborate the component. It has a scanner, parser and a builder. This last one is responsible for build the component, an object that can be manipulated in Python and simulates the behavior of the integrated circuit. The model object it's a set of signals buses and uses event driven algorithm and dynamic programming to simulate the behavior of the circuit.

Using the HLS side, you can create the component "by hand". Also with the use of the Python package you can manipulate the signals and sava then in a waveform file.

Grammar and Syntax

The language is defined by the EBNF findable here.

🚀 Release

Flote is in beta development. You can see the latest releases in the GitHub repository.

📝 To Do List

To finish the beta version, the following tasks need to be completed:

• Make the simulation class (Component)
• Make EBNF for the language
• Make Scanner
• Make Parser
• Make Builder
• Make Testbench class to encapsulate the simulation component
• Make accept expressions
• Improve the algorithm of simulation (n² -> n+e)
• Improve declaration to accept assignment
• Create signal class for waveform dump
• Create waveform dump feature
• Improve semantic errors by adding error line
• Improve methods of Testbench
• Publish initial beta package in PyPI
• Add multi-dimensional bit signals support
  • Declaration
  • Assignment
  • Operation
  • Error handling for declaration and assignment
  • .vcd dump support for multi-dimensional bit signals
  • Indexing
  • Slicing
  • Error handling for indexing and slicing
  • Concatenation
  • Big endian support
  • N-Dimensional arrays support with concatenation
• Add sub-components support
  • Instantiation
  • Connection
  • Error handling for instantiation and connection
  • .vcd dump support for sub-components
• Implement Rust backend for faster simulation
  • Connect Python with Rust using pyo3 and maturin
  • Create IR (Intermediate Representation) to communicate frontend with backend
  • Implement the IR render to use the Python backend previously created
  • Implement the Rust backend
• Improve README
• Make automated tests
• Create GitHub Actions for CI/CD
• Create documentation
• Create site with GitHub Pages

For future releases, the following features are planned:

• Create import feature
• Create std libs
• Add generate statement support
• Add multi-assignment support
• Add in-out signals support
• Add xbit(0, 1, x, z) support
• Implement custom types feature
• Add Python calls support
• Improve HLS support
• Add manual time control