An open-source HDL register generator fast enough to run in real time
The hdl_registers project is an open-source HDL register generator fast enough to run in real time. It can easily be plugged into your development environment so that VHDL register code generation is done before each build and simulation. For your FPGA release artifacts it can generate headers and documentation.
See documentation on the website: https://hdl-registers.com
Check out the source code on gitlab: https://gitlab.com/hdl_registers/hdl_registers
The typical use case is to let hdl_registers parse a .toml file with register definitions. Alternatively, one can also work directly with the Python abstractions without using a data file. The following code can be generated by the tool:
VHDL package with register/field definitions and types. To be used with a generic register file in your VHDL code.
HTML website with documentation of registers and fields.
C header with register addresses and field information.
C++ header and implementation with setters/getters for registers and fields. The header has an abstract interface class which can be used for mocking.
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