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IP-core package generator for AXI4/Avalon

Project Description


IP-core package generator for AXI4/Avalon

Copyright (C) 2015, Shinya Takamaeda-Yamazaki



Apache License 2.0 (


If you use IPgen in your research, please cite my paper about Pyverilog. (IPgen is constructed on Pyverilog.)

  • Shinya Takamaeda-Yamazaki: Pyverilog: A Python-based Hardware Design Processing Toolkit for Verilog HDL, 11th International Symposium on Applied Reconfigurable Computing (ARC 2015) (Poster), Lecture Notes in Computer Science, Vol.9040/2015, pp.451-460, April 2015. Paper
title={Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL},
author={Takamaeda-Yamazaki, Shinya},
booktitle={Applied Reconfigurable Computing},
series={Lecture Notes in Computer Science},
publisher={Springer International Publishing},

What’s IPgen?

IPgen is a lightweight IP-core package synthesizer from abstract RTL sources. You can implement both AXI4 and Avalon IP-core by using the provided abstract interfaces.

  • ipgen_master_memory: memory-mapped access interface (master)
  • ipgen_slave_memory: memory-mapped access interface (slave)
  • ipgen_master_lite_memory: memory-mapped access lite interface (master)
  • ipgen_slave_lite_memory: memory-mapped access lite interface (slave)



  • Python: 2.7, 3.4 or later

Python3 is recommended.

  • Icarus Verilog: 0.9.7 or later

Install on your platform. For exmple, on Ubuntu:

sudo apt-get install iverilog
  • Jinja2: 2.8 or later
  • pytest: 2.8.2 or later
  • pytest-pythonpath: 0.7 or later

Install on your python environment by using pip.

pip install jinja2 pytest pytest-pythonpath
  • Pyverilog: 1.1.1 or later

Install from pip:

pip install pyverilog


Install IPgen.

python install

Getting Started

You can use the ipgen command from your console.


You can find the sample projects in ‘tests’. Now let’s see ‘tests/memcpy’. There is an input source code.

  • memcpy.v : User-defined Verilog code using IPgen abstract memory interfaces

Then type ‘make’ and ‘make run’ to simulate sample system.

make build
make sim

Or type commands as below directly.

ipgen default.config -t memcpy -I include tests/memcpy/memcpy.v
iverilog -I memcpy_ip_v1_00_a/hdl/verilog/ memcpy_ip_v1_00_a/test/test_memcpy_ip.v

IPgen compiler generates a directory for IP-core (memcpy_ip_v1_00_a, in this example).

‘memcpy_ip_v1_00_a.v’ includes - IP-core RTL design (hdl/verilog/memcpy_ip.v) - Test bench (test/test_memcpy_ip.v) - XPS setting files (memcpy_ip_v2_1_0.{mpd,pao,tcl}) - IP-XACT file (component.xml)

A bit-stream can be synthesized by using Xilinx Platform Studio, Xilinx Vivado, and Altera Qsys. In case of XPS, please copy the generated IP-core into ‘pcores’ directory of XPS project.

IPgen Command Options


ipgen [config] [-t topmodule] [--ipname=ipname] [--memimg=memimg_name] [--usertest=usertest_name] [-I include]+ [-D define]+ [file]+


  • config
    • System configuration file which includes memory and device specifications
  • -t
    • Top-module name of user logic, default: ‘top’
  • –ipname
    • IP-core package name, default: ‘(topmodule)*ip*(version)’
  • –memimg
    • Memory image file in HEX (option). The file is copied into test directory. If no file is assigned, the array is initialized with incremental values.
  • –usertest
    • User-defined test code file (option). The code is copied into testbench script.
  • -I
    • Include path
  • -D
    • Macro definition
  • file
    • User-logic Verilog file (.v)

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