LabVIEW FPGA HDL Tools

Command-line tools (nihdl) for building customized FPGA designs for use with the ni/flexrio repository. They move, generate, and process the files needed to take a top-level HDL design to a LabVIEW FPGA bitfile through either of two compile flows (see below).

Customizing a FlexRIO board? Start at flexrio-custom, not here. That repo is the front door — supported devices, machine setup, and the step-by-step exercises. This page is the tool reference for the nihdl toolchain (commands, settings, and the concepts behind them); use it to look things up while following the flexrio-custom workflows.

The two compile flows

nihdl supports two ways to turn a top-level HDL design into a LabVIEW FPGA bitfile. Both start by extending the board's open-source top-level HDL, and both run Vivado in the end — they differ in what compiles the bitfile:

• Vivado compile flow — extend the design in HDL and compile the bitfile directly in Vivado (gen-vivado → compile-vivado). The host talks to your logic over registers and DMA FIFOs via the NI-RIO driver — no LabVIEW required.
• LabVIEW FPGA compile flow — package your HDL as a custom LabVIEW FPGA target (gen-target → install-target), then write a VI and let LabVIEW FPGA compile the bitfile (it runs Vivado under the hood).

Host-side note: to communicate with the compiled .lvbitx from a LabVIEW FPGA host VI, open it with Open Dynamic Bitfile Reference (wire in the bitfile path and a matching FPGA Interface Dynamic Refnum) — the standard Open FPGA VI Reference node does not work with these custom targets. See Vivado Compile Flow → Opening the bitfile from a LabVIEW FPGA host VI.

In short: in the Vivado flow you drive Vivado; in the LabVIEW FPGA flow LabVIEW FPGA drives Vivado for you. See Theory of Operation for the full story.

Documentation

Prerequisites

External tools

You need the external tools your flow uses:

• Vivado — for gen-vivado, check-vivado, and compile-vivado (use the version your FlexRIO release targets).
• LabVIEW + LabVIEW FPGA and the LabVIEW FPGA Compilation Tool for Vivado — for gen-lvbitx and custom LabVIEW FPGA targets.
• ModelSim — only for simulation (gen-modelsim, sim-modelsim, launch-modelsim, compile-modelsim-lib). compile-modelsim-lib also needs Vivado to compile the Xilinx simulation libraries.
• Git and Python — the tools support Python 3.10–3.14; CI tests on 3.10 through 3.14 (3.11 is also used for static analysis).

Installing the tools

nihdl is published to PyPI and is normally installed into a per-target Python virtual environment by the host repository's setup script. From a target folder that contains nihdlsettings.py (for example, c:/dev/github/flexrio-custom/targets/pxie-7903custom), run:

nisetup

This creates and activates a virtual environment and installs the version of labview-fpga-hdl-tools pinned in the repository's dependencies.toml. Re-run nisetup in every new terminal — the environment is only active for the current session, and you'll see the environment name (for example, (flexrio-custom)) in your prompt when it is active.

To install the package directly instead (for example, outside a flexrio-custom checkout):

pip install labview-fpga-hdl-tools

Required Files

Every target folder must contain a nihdlsettings.py file. It configures all paths, tool locations, and project settings via setter calls, and defines hook functions that run before/after each command. The CLI exits with an error if it is not found.

A complete starter template lives at labview_fpga_hdl_tools/nihdlsettings_default.py — copy it into your target folder as nihdlsettings.py and customize it. See the Settings Reference for details.

All nihdl commands are run from the target folder unless noted otherwise:

nihdl --help

By default nihdl prints results inline and collects any warnings and errors into a single summary at the end. Add -v (--verbose) to any command for full step-by-step status with warnings and errors also shown inline; the end summary still appears, so verbose is additive to the default. See the Command Reference for details.

Quickstart: the Vivado compile flow (tool-only)

Using flexrio-custom? Follow its Getting Started exercises instead — they are the canonical command sequence for that repo. This quickstart is for driving nihdl standalone (installed via pip, outside a flexrio-custom checkout).

Run these from your target folder (the one with nihdlsettings.py), with the Python environment active (run nisetup once per terminal — see Prerequisites):

# 1. Pull in GitHub dependencies declared in dependencies.toml
nihdl install-deps

# 2. Create the Vivado project from your settings + HDL file lists
#    (this also runs gen-hdl and gen-xdc automatically)
nihdl gen-vivado --overwrite

# 3. Fast RTL elaboration check before a full compile
nihdl check-vivado

# 4. Full compile to a bitstream and LabVIEW FPGA bitfile
#    (this runs gen-lvbitx automatically at the end)
nihdl compile-vivado

Open the project interactively at any point with nihdl launch-vivado.

Full walkthrough: Vivado Compile Flow.

The LabVIEW FPGA compile flow (custom target)

To expose your HDL to LabVIEW FPGA as a custom target, define your I/O in the custom I/O CSV, then:

# Generate target support files (BoardIO/Clock XML, Window VHDL, plugin content)
nihdl gen-target

# Close ALL LabVIEW instances, then install the generated plugin into your LabVIEW FPGA install
nihdl install-target

Close LabVIEW around install-target. Close all LabVIEW instances before running it, and (re)start LabVIEW afterward — LabVIEW only scans for target plugins at startup.

Full walkthrough: LabVIEW FPGA Target and Compile Flow.

Simulating with ModelSim

# Create the ModelSim project and compile all VHDL, then run the testbench
nihdl gen-modelsim --overwrite
nihdl sim-modelsim        # or: nihdl launch-modelsim  (GUI; --batch for headless)

Full walkthrough: ModelSim Simulation Flow — including the Xilinx simulation libraries and how the pass/fail verdict works.

For the complete command list, options, and required settings, see the Command Reference.

Validating Without External Tools

To exercise settings and file generation without launching Vivado or ModelSim, set skip flags in your nihdlsettings.py:

def pre_all(context):
    config = context.config
    # ... configure settings ...
    config.set_skip_vivado(True)
    config.set_skip_modelsim(True)

Troubleshooting / FAQ

Error: Settings file not found: ...nihdlsettings.py Run the command from the target folder that contains nihdlsettings.py, or pass --config path/to/nihdlsettings.py.

A command reports a missing required setting. Each command validates the settings it needs before running. Check the Per-Command Setting Requirements table and confirm the corresponding setter is called in pre_all(). Remember that relative paths resolve from the nihdlsettings.py file's directory.

A relative path isn't resolving the way I expect. All hooks run with the working directory set to the nihdlsettings.py file's directory, and path setters resolve relative paths from there. Use forward slashes (/) on every platform.

launch-vivado / check-vivado / compile-vivado can't find the project. Run nihdl gen-vivado --overwrite first; these commands require an existing .xpr.

gen-lvbitx warns it isn't in the right place. It is intended to run from VivadoProject/<project>.runs/impl_1. It also needs to locate createBitfile.exe; it auto-discovers the latest installed LabVIEW (2023–2030), or set set_labview_path(...) to point at a specific install.

A dependency file collides by name with a target-specific copy. Use add_exclude_hdl_file_list(...) to drop the unwanted copy from the assembled HDL file list.