najaeda
najaeda is a Python package for loading, elaborating, navigating, editing, and analysing hardware designs from gate-level Verilog netlists to large SystemVerilog RTL cores.
from najaeda import netlist
# Load a gate-level Verilog design with a Liberty standard-cell library
netlist.load_liberty(['NangateOpenCellLibrary.lib'])
top = netlist.load_gate_level_verilog('my_design.v')
# Navigate the hierarchy
for inst in top.get_child_instances():
print(f'{inst.get_name()} → {inst.get_model_name()}')
# Flat connectivity across hierarchy boundaries
for iterm in top.get_term('clk').get_equipotential().get_inst_terms():
print(iterm)
# Edit: rename, reconnect, delete
top.get_net('old_name').set_name('new_name')What you can do
Load gate-level Verilog netlists and elaborate supported Verilog/SystemVerilog RTL, with or without Liberty standard-cell libraries
Navigate hierarchy, nets, and ports at any level of detail — instance-by-instance or flat via equipotentials
Edit netlists: rename instances and nets, disconnect and reconnect signals, delete logic
Analyse designs with the visitor API and export results to pandas for further processing or visualisation
Installation
pip install najaedaFor the optional schematic viewer, run pip install "najaeda[schematic]". In a notebook, use from najaeda.schematic import show; show() to display the currently loaded design.
Requires Python 3.10 or later. Pre-built wheels are published for:
Linux x86_64 and AArch64 (manylinux_2_28; glibc 2.28 or later)
macOS Apple Silicon (arm64), macOS 11 or later
Windows x86_64
Building from a checkout
Initialize the submodules, install the native build dependencies (including Flex and Bison), then run python -m pip wheel .. Parser-source selection is automatic: a Git checkout generates the Verilog parser, while release source distributions with bundled generated parser files use those files. An explicit -C cmake.define.PREGENERATED_PARSER_SOURCES=ON or OFF still overrides the selection; ON requires the bundled files to exist.
Tutorials
Six hands-on notebooks — open any of them in Google Colab with no local install needed:
# |
Topic |
Colab |
|---|---|---|
1 |
Getting started — load Verilog, navigate hierarchy, visualize |
|
2 |
Liberty primitives — load a synthesised design with standard cells |
|
3 |
Editing a netlist — rename, disconnect, reconnect, delete |
|
4 |
SystemVerilog elaboration — load and browse an elaborated SV design |
|
5 |
ibex RISC-V core — explore a real-world SV core, collect module stats |
|
6 |
Fanout analysis — compute fanout for every net, trace drivers, export to pandas |
|
Links
License
Apache License 2.0. See the LICENSE file for details.
1 maintainer
Metadata
1 maintainer
Release files for najaeda 0.7.34
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