An abstract language model of SystemVerilog (incl. Verilog) written in Python.
Main Goals
This package provides a unified abstract language model for SystemVerilog (incl. Verilog). Projects reading from source files can derive own classes and implement additional logic to create a concrete language model for their tools.
Projects consuming pre-processed System Verilog data (parsed, analyzed or elaborated) can build higher level features and services on such a model, while supporting multiple frontends.
Use Cases
pySVModel Generators
TBD
pySVModel Consumers
TBD
Examples
List all Modules with Parameters and Ports
TBD
Contributors
- Patrick Lehmann (Maintainer)
- Unai Martinez-Corral
- and more...
License
This Python package (source code) is licensed under Apache License 2.0.
The accompanying documentation is licensed under Creative Commons - Attribution 4.0 (CC-BY 4.0).
SPDX-License-Identifier: Apache-2.0
Release files for pySVModel 0.5.11
For a detailed explanation of source distributions (sdists) and built distributions (wheels), please see the package formats documentation.
Source distribution (sdist)
| File | Size | Uploaded | |
|---|---|---|---|
| pysvmodel-0.5.11.tar.gz | 11.4 kB | Details |
Built distribution (wheel)
| File | Interpreter | ABI | Platform | Reset |
|---|---|---|---|---|
| pysvmodel-0.5.11-py3-none-any.whl | Python 3 | none | any | Details |
Total release size: 21.4 kB
Release files / pysvmodel-0.5.11.tar.gz
| Download URL | pysvmodel-0.5.11.tar.gz |
|---|---|
| Size | 11.4 kB |
| Tags | Source |
|
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Release files / pysvmodel-0.5.11-py3-none-any.whl
| Download URL | pysvmodel-0.5.11-py3-none-any.whl |
|---|---|
| Size | 10.0 kB |
| Tags | Python 3 |
|
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| Uploaded via |
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