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RTLViz

Generate interactive block diagrams from Verilog source files.

Python License

Installation

Step 1: Install Package

pip install rtlviz

Step 2: Setup IDE

Spins up the MCP server config for all popular IDEs.

rtlviz setup

Step 3: Manual IDE Setup (if Step 2 fails)

If the automatic setup doesn't work, you can manually configure your IDE's MCP settings (e.g., claude_desktop_config.json).

Command: rtlviz-server works if installed in PATH. Otherwise use python -m rtlviz.

JSON Config:

{
  "mcpServers": {
    "rtlviz": {
      "command": "python",
      "args": ["-m", "rtlviz"]
    }
  }
}

Usage

AI Agent

After setup, ask your AI assistant (Role: Software Engineer):

"Use rtlviz MCP to generate a diagram for the Verilog files in <path to code>"

The diagram will automatically open in your browser.

Recommended Models: For best results, use state-of-the-art reasoning models:

  • Claude: Opus 4.5 , Sonnet 4.5
  • Google: Gemini 3
  • OpenAI: GPT-5.2

Example Output

RISC-V CPU Block Diagram

Features

  • Automatic Parsing - Extractions modules and connections from Verilog
  • Pipeline Detection - Identifies CPU stages (IF, ID, EX, MEM, WB)
  • Beautiful Diagrams - Orthogonal routing with semantic clustering
  • Interactive - Pan, zoom, and export to SVG
  • Auto-Open - Instantly opens generated diagrams in browser

Requirements

  • Python 3.10+
  • Internet connection (for Viz.js rendering)

Authors

License

MIT License

Metadata

Release files for rtlviz 0.9.0

For a detailed explanation of source distributions (sdists) and built distributions (wheels), please see the package formats documentation.

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Source distribution for rtlviz 0.9.0
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Table of built distributions (wheels) for rtlviz 0.9.0
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rtlviz-0.9.0-py3-none-any.whl Python 3 none any Details

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