A set of tools for developing RISC-V Vector IP includes Random Test Generator (RTG), Assembler, and Simulator
Project description
RISC-V Vector Development Suite
A set of tools for developing RISC-V Vector IP includes Random Test Generator (RTG), Assembler, and Simulator.
This project is not yet complete.
However, since my teammate needs it for testing the RTL design, I have decided to publish it anyway.
Changelog
| Version | Description | Owner |
|---|---|---|
| 0.0.1 | Initial version | Nguyen Binh Khiem |
| 0.0.2 | Fix SRA operator of ICB | Nguyen Binh Khiem |
| 0.0.3 | Ignore out-of-width address bits in vector load and store instructions | Nguyen Binh Khiem |
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