A set of tools for developing RISC-V Vector IP includes Random Test Generator (RTG), Assembler, and Simulator
Project description
RISC-V Vector Development Suite
A set of tools for developing RISC-V Vector IP includes Random Test Generator (RTG), Assembler, and Simulator.
This project is not yet complete.
However, since my teammate needs it for testing the RTL design, I have decided to publish it anyway.
Supported features
Configurations
APIs
Changelog
Version 0.0.5 (by Nguyen Binh Khiem)
- [Fixed]
SimulatorFixed vector load operations.
Version 0.0.4 (by Nguyen Binh Khiem)
- [Changed]
SimulatorModified how PC is logged. - [Changed]
SimulatorAdded debug mode. - [Fixed]
SimulatorFixed vector store operations.
Version 0.0.3 (by Nguyen Binh Khiem)
- [Changed]
SimulatorIgnored out-of-width address bits in vector load and store instructions in simulator.
Version 0.0.2 (by Nguyen Binh Khiem)
- [Fixed]
SimulatorFixed SRA opeator of ICB
Version 0.0.1 (by Nguyen Binh Khiem)
- [Added] Initial version
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