A project platform for modern FPGA development
This repo contains a set of tools for working in a modern FPGA project.
See documentation on the website: https://truestream.gitlab.io/tsfpga
It consists of two distinct parts that can be used independently of each other.
A project platform for FPGA development
tsfpga folder contains a Python package for working with modules and FPGA build projects.
The goal is a highly useable system for working in a multi-chip and multi-vendor environment.
Focus has been placed on modularization and enabling a high level of scalability.
- Source code centric project structure: Constraints, IP cores, test configurations, build projects, etc. are handled "close" to the source code. See e.g. resync_counter.tcl, mult_u12_u5.tcl, module_math.py, project_artyz7.py.
- Generic AXI-Lite register file, with automatic register generation from JSON: VHDL package, C header, C++ class, HTML documentation. See e.g. ddr_buffer_regs.json and build.py.
- Automatic (re)compile of simlib and IP core simulation files. See e.g. vivado_simlib.py, vivado_ip_cores.py and simulate.py.
In order to use the package you will need
- Python 3.6+
- VUnit in your
PYTHONPATH, with a functioning VHDL simulator in your
- Python package:
To run the bundled tests you must have
- Python packages:
- Xilinx Vivado 2018.3+ in your
- GCC in your
A reusable set of HDL building blocks
modules folder contains a set of VHDL modules/IP that are common in many FPGA projects.
The modules have been developed with quality and reusability in mind.
Having these high quality building blocks available will make it easier to add new functionality to your project.
The modules make heavy use of
VHDL-2008 so you will need a recent simulator and synthesis tool.
- Olof Kraigher
- Ludvig Vidlid
- Lukas Vik
This project is released under the terms of the BSD 3-Clause License. See
license.txt for details.
Download the file for your platform. If you're not sure which to choose, learn more about installing packages.
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