xeda 0.2.10

Cross EDA Abstraction and Automation

Xeda /ˈziːdə/ is a cross-platform, cross-EDA, cross-target simulation and synthesis automation platform. It assists hardware developers in verification, evaluation, and deployment of RTL designs. Xeda supports flows from multiple commercial and open-source electronic design automation suites.

Xeda is the one tool to rule 'em all!

For further details, visit the Xeda's documentations (Work In Progress).

Installation

Python 3.9 or newer is required. You can install the latest published version from pypi. If you only need the command line interface, you can install xeda using pipx.

pipx install --force xeda

If you want to use Xeda in a virtual environment, you can install it using pip:

python3 -m pip install -U xeda

Development

git clone --recursive https://github.com/XedaHQ/xeda.git
cd xeda
python3 -m venv venv
source venv/bin/activate
python3 -m pip install -U pip setuptools wheel
python3 -m pip install -U --editable .

Usage

Run xeda --help to see a list of available commands and options.

Design Description

Xeda design-specific descriptions and settings are organized through project files specified in TOML. Every project contains one or more HDL designs. The default name for the project file is xedaproject.toml.

Sample Xeda design description file in YAML format:

hdl.vhdl.standard: 2008

sources:
    - trivium.vhdl
parameters:
  G_IN_BITS: 64
  G_OUT_BITS: 64
  G_SETUP_ROUNDS: 4
top: trivium
clock.port: clk

test:
  sources:
  - trivium_tb.py
  - cref/trivium64.c

flows:
  vivado_synth:
    fpga.part: xc7a12tcsg325-3
    clock.freq: 200MHz
  dc:
    target_libraries:
      - $PWD/lib/SAED90/saed90nm_typ_ht.db

Sample Xeda design description file in TOML format:

name = "sqrt"
description = "Iterative computation of square-root of an integer"
language.vhdl.standard = "2008"

[rtl]
sources = ["sqrt.vhdl"]
top = "sqrt"
clock_port = "clk"
parameters = { G_IN_WIDTH = 32 }

[tb]
sources = ["tb_sqrt.py"]
cocotb = true

[flows.vivado_synth]
fpga.part = 'xc7a12tcsg325-1'
clock_period = 5.0

Flows

A Tool is an abstraction for an executable which is responsible for one or several steps in an EDA flow. A Tool can be executed as a native binary already installed on the system, in a virtualized container (e.g. docker), or on a remote system. A Flow is a collection of steps performed by one or several tools. A Xeda Flow implements the following methods:

• init(optional): initializations which need to happen after the instantiation of a Flow instance. At this stage, the flow can specify and customize dependency flows, which will be run before execution of the flow. Seperation of this stage form Python __init__ enables greater flexibility and more effective control over the execution of flows.
• run: main execution of the flow which includes generation of files, scripts, and tool arguments as well as execution of one or several tools. All dependencies have been already executed before run begins, and the completed dependencies (and their results and artifacts) will be available.
• parse_results(optional): evaluate and interpret generated reports or other artifacts.

Supported Tools and Flows

• AMD-Xilinx Vivado Design Suite
  • vivado_synth: FPGA synthesis and implementation.
  • vivado_sim: functional simulation of RTL design
  • vivado_postsynthsim: Post-implementation functional and timing simulation and power analysis
  • vivado_power: Post-implementation power estimation based on post-implementation timing simulation with real-world target testvectors
• AMD-Xilinx ISE Design Suite
• GHDL VHDL simulator
  • ghdl_sim
• Intel Quartus Prime (Lite/Pro Editions):
  • quartus: FPGA synthesis and implementation flow
• Lattice Diamond
  • diamond_synth: FPGA synthesis and implementation flow
• Mentor (Siemens) ModelSim
  • modelsim RTL and netlist simulation
• nextpnr portable FPGA place and route tool
• openFPGAloader: Open-source and multi-platform universal utility for programming FPGAs. Compatible with many boards, cables and FPGA from major manufacturers.
• OpenROAD: integrated chip physical design flow that takes a design from RTL sources to routed layout.
• Synopsys Design Compiler
• Synopsys VCS simulator
• Verilator: the fastest (open-source) Verilog/SystemVerilog simulator.
• Bluespec: Compiler, simulator, and tools for the Bluespec Hardware Description Language.
• Yosys Open SYnthesis Suite (FPGA and ASICs synthesis)

Run xeda list-flows for the full list of supported flows in the installed version.