10 projects
peakrdl-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block
peakrdl-html
HTML documentation generator for SystemRDL-based register models
peakrdl-uvm
Generate UVM register model from compiled SystemRDL input
peakrdl-ipxact
Import and export IP-XACT XML to/from the systemrdl-compiler register model
systemrdl-compiler
Parse and elaborate front-end for SystemRDL 2.0
speedy-antlr-tool
Generate an accelerator extension that makes your Antlr parser in Python super-fast!
git-me-the-url
Generate sharable links to your Git source
pygments-systemrdl
SystemRDL 2.0 lexer extension for Pygments
ralbot-uvm
Generate UVM register model from compiled SystemRDL input
peakrdl
Command-line tool for control/status register automation