Axion-HDL
AXI4-Lite register interfaces from VHDL, SystemVerilog, YAML, TOML, XML, or JSON. One command.
Install
For users:
pip install axion-hdl
For development:
git clone https://github.com/bugratufan/axion-hdl.git
cd axion-hdl
python3 -m venv venv
source venv/bin/activate
pip install -e ".[dev]" # Includes pytest, cocotb, etc.
Use
# From VHDL with @axion annotations
axion-hdl -s my_module.vhd -o output/
# From SystemVerilog with @axion annotations
axion-hdl -s my_module.sv -o output/
# From YAML/TOML/XML/JSON
axion-hdl -s registers.yaml -o output/
axion-hdl -s registers.toml -o output/
Output: VHDL/SystemVerilog modules, C headers, documentation, YAML/TOML/XML/JSON exports.
Define Registers
VHDL — embed in your code:
-- @axion_def BASE_ADDR=0x1000 CDC_EN
signal status : std_logic_vector(31 downto 0); -- @axion RO
signal control : std_logic_vector(31 downto 0); -- @axion RW W_STROBE
SystemVerilog — same annotations, different syntax:
// @axion_def BASE_ADDR=0x1000 CDC_EN
logic [31:0] status; // @axion RO
logic [31:0] control; // @axion RW W_STROBE
YAML — standalone file:
module: my_module
base_addr: "0x1000"
config:
cdc_en: true
registers:
- name: status
access: RO
- name: control
access: RW
w_strobe: true
TOML — clean, readable syntax:
module = "spi_master"
base_addr = "0x0000"
[config]
cdc_en = true
cdc_stage = 2
[[registers]]
name = "control"
addr = "0x00"
access = "RW"
w_strobe = true
description = "SPI control register"
[[registers]]
name = "status"
addr = "0x04"
access = "RO"
r_strobe = true
description = "SPI status register"
Output — one command:
axion-hdl -s spi_master.toml -o output --all
Generates: VHDL + SystemVerilog modules, C header, HTML docs, YAML/TOML/XML/JSON exports
Features
- Multi-format input — VHDL/SystemVerilog annotations, YAML, TOML, XML, JSON
- Multi-HDL output — Generate both VHDL and SystemVerilog register interfaces
- CDC support — built-in clock domain crossing synchronizers
- XDC constraints — instance-independent Vivado false-path constraints per module (
--xdc) - Subregisters — pack multiple fields into one address
- Wide signals — auto-split 64-bit+ signals across addresses
- Tested — 307+ tests, GHDL simulation verified
Documentation
Development & Testing
Quick start:
git clone https://github.com/bugratufan/axion-hdl.git
cd axion-hdl
make test # Auto-installs dependencies and runs all tests
The make test command automatically:
- Creates a virtual environment if needed
- Installs all test dependencies
- Runs 307+ tests (Python + VHDL + cocotb)
Note: For SystemVerilog linting tests,
verilatormust be installed on your system (sudo apt install verilator) formake testto pass.
Manual setup (optional):
make setup-dev # Create venv + install dependencies
source venv/bin/activate
CI/Automated environments:
AXION_AUTO_INSTALL=1 make test # Skip prompt, auto-install
Contributing:
git checkout develop
git checkout -b feature/your-feature
# Make changes
make test # Dependencies auto-installed on first run
# Submit PR to develop branch
License
MIT — Bugra Tufan
1 maintainer
Metadata
1 maintainer
Release files for axion-hdl 1.7.1
For a detailed explanation of source distributions (sdists) and built distributions (wheels), please see the package formats documentation.
Source distribution (sdist)
| File | Size | Uploaded | |
|---|---|---|---|
| axion_hdl-1.7.1.tar.gz | 393.1 kB | Details |
Built distribution (wheel)
| File | Interpreter | ABI | Platform | Reset |
|---|---|---|---|---|
| axion_hdl-1.7.1-py3-none-any.whl | Python 3 | none | any | Details |
Total release size: 623.3 kB
Release files / axion_hdl-1.7.1.tar.gz
| Download URL | axion_hdl-1.7.1.tar.gz |
|---|---|
| Size | 393.1 kB |
| Tags | Source |
|
SHA-256 checksum How to use checksums |
73f9dede9e927196ee9e8177aa9392150fa14566ad3840952f084e514ade4c41
|
|
BLAKE2b-256 checksum How to use checksums |
229f3741d03786571cbd3f408d60e34d2d63cc7b89e2d3c8f9a01e546ebe2e08
|
| Upload date | |
|
Uploaded using Trusted Publishing? What is trusted publishing? |
Yes |
| Uploaded via |
twine/6.1.0 CPython/3.13.14
|
Provenance
Provenance describes where a file came from. On PyPI, provenance is shared via attestations, which provide a verifiable record of the build or publishing details. View details, limitations and caveats.
PyPI Publish Attestation
PyPI verified that this artifact, at this checksum, originated from the publisher listed below.
Signed by GitHub Actions, verified by PyPI on Jul 27, 2026.
Transparency logRelease files / axion_hdl-1.7.1-py3-none-any.whl
| Download URL | axion_hdl-1.7.1-py3-none-any.whl |
|---|---|
| Size | 230.2 kB |
| Tags | Python 3 |
|
SHA-256 checksum How to use checksums |
b0570109da9866d68d2c619cfe50345fd5a68f6a6e8314efadae4b64aa8bbdbb
|
|
BLAKE2b-256 checksum How to use checksums |
60b34f6b14a9465ab5ed8f4512434d35698fe4cd66f028f3ef5a718ac70aa902
|
| Upload date | |
|
Uploaded using Trusted Publishing? What is trusted publishing? |
Yes |
| Uploaded via |
twine/6.1.0 CPython/3.13.14
|
Provenance
Provenance describes where a file came from. On PyPI, provenance is shared via attestations, which provide a verifiable record of the build or publishing details. View details, limitations and caveats.
PyPI Publish Attestation
PyPI verified that this artifact, at this checksum, originated from the publisher listed below.
Signed by GitHub Actions, verified by PyPI on Jul 27, 2026.
Transparency log
