axion-hdl 0.6.3

Automated AXI4-Lite Register Interface Generator for VHDL modules

Axion-HDL

AXI4-Lite register interfaces from VHDL, YAML, XML, or JSON. One command.

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Install

pip install axion-hdl

Use

# From VHDL with @axion annotations
axion-hdl -s my_module.vhd -o output/

# From YAML/XML/JSON
axion-hdl -s registers.yaml -o output/

Output: VHDL module, C header, documentation, XML/YAML/JSON exports.

Define Registers

VHDL — embed in your code:

-- @axion_def BASE_ADDR=0x1000 CDC_EN
signal status  : std_logic_vector(31 downto 0); -- @axion RO
signal control : std_logic_vector(31 downto 0); -- @axion RW W_STROBE

YAML — standalone file:

module: my_module
base_addr: "0x1000"
config:
  cdc_en: true
registers:
  - name: status
    access: RO
  - name: control
    access: RW
    w_strobe: true

Features

• Multi-format input — VHDL annotations, YAML, XML, JSON
• CDC support — built-in clock domain crossing synchronizers
• Subregisters — pack multiple fields into one address
• Wide signals — auto-split 64-bit+ signals across addresses
• Tested — 230+ tests, GHDL simulation verified

Documentation

📖 axion-hdl.readthedocs.io

Contributing

git checkout develop
git checkout -b feature/your-feature
make test
# PR to develop

License

MIT — Bugra Tufan