Command-line tool for control/status register automation and code generation.

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License: GNU General Public License v3 (GPLv3) (GNU GENERAL PUBLIC LICENSE Version 3, 29 June 2007 Copyright (C) 2007 Free Software Foundation, Inc...)

Author: Alex Mykyta

Tags SystmRDL, PeakRDL, CSR, compiler, tool, registers, generator, C, header, software, Verilog, SystemVerilog, register abstraction layer, FPGA, ASIC

Requires: Python >=3.6

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PeakRDL

PeakRDL is a free and open-source control & status register (CSR) toolchain. This project provides a command-line tool that unifies many aspects of register automation centered around the SystemRDL register description language.

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See the PeakRDL Documentation for more details.

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License: GNU General Public License v3 (GPLv3) (GNU GENERAL PUBLIC LICENSE Version 3, 29 June 2007 Copyright (C) 2007 Free Software Foundation, Inc...)

Author: Alex Mykyta

Tags SystmRDL, PeakRDL, CSR, compiler, tool, registers, generator, C, header, software, Verilog, SystemVerilog, register abstraction layer, FPGA, ASIC

Requires: Python >=3.6

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