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High Level Synthesis tool for FPGA using NoCs.

Project Description
SyntheSys
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SyntheSys is a Python module for generating network on chip (NoC) based systems from Python3 programs. It is specially design for reconfigurable computing, i.e. using FPGA to accelerate parts of programs. It has a extensible library for any type of FPGA and uses NoC properties to be scalable.

This is the README file for the project.

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SyntheSys is distributed with a GPLv3 license.
See LICENSE.txt for details.
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Matthieu PAYET <matthieu.payet@free.fr>
More on Matthieu's website : mpayet.net
Release History

Release History

This version
History Node

0.1.1

History Node

0.1

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File Name & Checksum SHA256 Checksum Help Version File Type Upload Date
SyntheSys-0.1.1.linux-x86_64.tar.gz (8.9 MB) Copy SHA256 Checksum SHA256 Source Jul 10, 2017
SyntheSys-0.1.1-py3-none-any.whl (9.1 MB) Copy SHA256 Checksum SHA256 py3 Wheel Jul 10, 2017

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