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Project Description

SyntheSys is a Python module for generating network on chip (NoC) based systems from Python3 programs. It is specially design for reconfigurable computing, i.e. using FPGA to accelerate parts of programs. It has a extensible library for any type of FPGA and uses NoC properties to be scalable.

This is the README file for the project.

SyntheSys is distributed with a GPLv3 license.
See LICENSE.txt for details.

Matthieu PAYET <>
More on `Matthieu's website <>`_
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TODO: Figure out how to actually get changelog content.

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File Name & Checksum SHA256 Checksum Help Version File Type Upload Date
SyntheSys-0.1-py3-none-any.whl (8.0 MB) Copy SHA256 Checksum SHA256 py3 Wheel Sep 23, 2016

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