sv-simpleparser 0.2.3

Easy-To-Use SystemVerilog Parser

Easy-To-Use SystemVerilog Parser

• PyPI
• Sources
• Issues

Features

• Extract Port Lists
• Extract Parameters
• Extract Submodule Instances
• ifdef support (planned)
• Standards: IEEE 1800-2009 SystemVerilog

Limitations

• No Syntax Checks - Source Code files must be syntactically correct
• No Full Parser - This parser intends to be simple and just extract some information from the source code. Fast and easy.

Installation

Installing it is pretty easy:

pip install sv-simpleparser

Usage

# Dump Markdown Table
sv-simpleparser info examples/adder.sv