Easy-To-Use SystemVerilog Parser

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  • Author: Eric Macedo
  • Tags SystemVerilog , Verilog , Parser
  • Requires: Python <4.0, >=3.10.0
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Project description

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Easy-To-Use SystemVerilog Parser

Features

  • Extract Port Lists
  • Extract Parameters
  • Extract Submodule Instances
  • ifdef support (planned)
  • Standards: IEEE 1800-2009 SystemVerilog

Limitations

  • No Syntax Checks - Source Code files must be syntactically correct
  • No Full Parser - This parser intends to be simple and just extract some information from the source code. Fast and easy.

Installation

Installing it is pretty easy:

pip install sv-simpleparser

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  • Author: Eric Macedo
  • Tags SystemVerilog , Verilog , Parser
  • Requires: Python <4.0, >=3.10.0
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0.5.2

0.5.1

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0.5.0

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0.0.0

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