Easy-To-Use SystemVerilog Parser

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  • Author: Eric Macedo
  • Tags SystemVerilog , Verilog , Parser
  • Requires: Python <4.0, >=3.10.0
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Easy-To-Use SystemVerilog Parser

Features

  • Extract Port Lists
  • Extract Parameters
  • Extract Submodule Instances and their connections
  • ifdef support
  • Standards: IEEE 1800-2009 SystemVerilog

Limitations

  • No Syntax Checks - Source Code files must be syntactically correct
  • No Full Parser - This parser intends to be simple and just extract some information from the source code. Fast and Simple.

Installation

Installing it is pretty easy:

pip install sv-simpleparser

Usage

See Usage Documentation

Project details

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  • Author: Eric Macedo
  • Tags SystemVerilog , Verilog , Parser
  • Requires: Python <4.0, >=3.10.0
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0.5.2

This version

0.5.1

0.5.0

0.4.3

0.4.2

0.4.1

0.4.0

0.3.0

0.2.3

0.2.1

0.2.0

0.1.0

0.0.11

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0.0.8

0.0.7

0.0.6

0.0.4

0.0.3

0.0.0

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